AD7277 Analog Devices, AD7277 Datasheet - Page 18

• Manufacturer Part Number: AD7277
• Description: 3 MSPS,10-Bit ADC in 6-Lead TSOT
• Manufacturer: Analog Devices

Specifications of AD7277

• Resolution (bits): 10bit
• # Chan: 1
• Sample Rate: 3MSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni Vdd
• Adc Architecture: SAR
• Pkg Type: SOP,SOT

AD7276/AD7277/AD7278
MODES OF OPERATION
The mode of operation of the AD7276/AD7277/AD7278 is
selected by controlling the logic state of the
conversion. There are three possible modes of operation: normal
mode, partial power-down mode, and full power-down mode.
The point at which
been initiated determines which power-down mode, if any, the
device enters. Similarly, if the device is already in power-down
mode,
operation or remains in power-down mode. These modes of
operation are designed to provide flexible power management
options, which can be chosen to optimize the power dissipation/
throughput rate ratio for different application requirements.
Normal Mode
This mode is intended for fastest throughput rate performance
because the device remains fully powered at all times, eliminating
worry about power-up times. Figure 24 shows the general diagram
of AD7276/AD7277/AD7278 operation in this mode.
The conversion is initiated on the falling edge of
in the
fully powered up at all times,
10 SCLK falling edges elapse after the falling edge of
brought high after the 10
SCLK falling edge, the part remains powered up, but the con-
version is terminated and SDATA goes back into three-state.
For the AD7276, a minimum of 14 serial clock cycles are required
to complete the conversion and access the complete conversion
result. For the AD7277 and AD7278, a minimum of 12 and
10 serial clock cycles are required to complete the conversion
and to access the complete conversion result, respectively.
Serial Interface
CS
can control whether the device returns to normal
CS
section. To ensure that the part remains
is pulled high after the conversion has
th
SDATA
SDATA
SCLK falling edge but before the 16
SCLK
SCLK
CS
CS
CS
must remain low until at least
1
1
CS
2
signal during a
CS
Figure 25. Entering Partial Power-Down Mode
as described
CS
Figure 24. Normal Mode Operation
. If
CS
Rev. C | Page 18 of 28
is
th
VALID DATA
10
CS
high before the next conversion (effectively idling
Once a data transfer is complete (SDATA has returned to three-
state), another conversion can be initiated after the quiet time,
t
Partial Power-Down Mode
This mode is intended for use in applications where slower
throughput rates are required. An example of this is when either
the ADC is powered down between each conversion or a series
of conversions is performed at a high throughput rate and then
the ADC is powered down for a relatively long duration between
these bursts of several conversions. When the AD7276/AD7277/
AD7278 are in partial power-down mode, all analog circuitry is
powered down except the bias-generation circuit.
To enter partial power-down mode, interrupt the conversion
process by bringing
edges of SCLK, as shown in
Once
enters partial power-down mode, the conversion that was
initiated by the falling edge of
goes back into three-state. If
second SCLK falling edge, the part remains in normal mode and
does not power down. This prevents accidental power-down due
to glitches on the
QUIET
10
can idle high until the next conversion or low until
THREE-STATE
, has elapsed by bringing
CS
12
is brought high in this window of SCLKs, the part
14
CS
CS
16
line.
AD7677/AD7278
high between the second and 10
16
AD7276/
Figure 25
CS
CS
CS
is brought high before the
low again.
is terminated, and SDATA
.
CS
CS
low).
th
returns
falling