AD7277 Analog Devices, AD7277 Datasheet - Page 8

• Manufacturer Part Number: AD7277
• Description: 3 MSPS,10-Bit ADC in 6-Lead TSOT
• Manufacturer: Analog Devices

Specifications of AD7277

• Resolution (bits): 10bit
• # Chan: 1
• Sample Rate: 3MSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni Vdd
• Adc Architecture: SAR
• Pkg Type: SOP,SOT

AD7276/AD7277/AD7278
Parameter
POWER REQUIREMENTS
1
2
3
4
5
TIMING SPECIFICATIONS—AD7276/AD7277/AD7278
V
Table 5.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
T
1
2
3
4
5
6
SCLK
CONVERT
QUIET
1
2
3
4
5
6
7
8
9
Temperature range from −40°C to +125°C.
Typical specifications are tested with V
See the Terminology section.
Guaranteed by characterization.
See the Power vs. Throughput Rate section.
Sample tested during initial release to ensure compliance. All timing specifications given are with a 10 pF load capacitance. With a load capacitance greater than this
value, a digital buffer or latch must be used.
Guaranteed by characterization. All input signals are specified with tr = tf = 2 ns (10% to 90% of V
Mark/space ratio for the SCLK input is 40/60 to 60/40.
Minimum f
The time required for the output to cross the V
See the Power-Up Times section.
POWER-UP
5
5
DD
5
V
I
Partial Power-Down Mode (Static)
Full Power-Down Mode (Static)
Power Dissipation
DD
DD
3
= 2.35 V to 3.6 V, T
Normal Mode (Static)
Normal Mode (Operational)
Normal Mode (Operational)
Partial Power-Down
Full Power-Down
6
SCLK
2
at which specifications are guaranteed.
Limit at T
500
48
16
14 × t
12 × t
10 × t
4
3
6
4
15
0.4 t
0.4 t
5
14
5
4.2
1
SCLK
SCLK
5
SCLK
SCLK
SCLK
A
MIN
= T
, T
MIN
MAX
to T
DD
= 3 V and at 25°C.
MAX
IH
, unless otherwise noted.
or V
IL
voltage.
Unit
kHz min
MHz max
MHz max
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
ns min
ns max
μs max
A Grade
2.35/3.6
0.5
5.5
3.5
34
2
10
19.8
10.5
102
7.2
4
1, 2
Rev. C | Page 8 of 28
1
B Grade
2.35/3.6
0.5
5.5
3.5
34
2
10
19.8
10.5
102
7.2
B grade
Y grade
AD7276
AD7277
AD7278
Minimum quiet time required between the bus relinquish and the
start of the next conversion
Minimum CS pulse width
CS to SCLK setup time
Delay from CS until SDATA three-state disabled
SCLK low pulse width
CS rising edge to SDATA three-state
Description
Data access time after SCLK falling edge
SCLK high pulse width
SCLK to data valid hold time
SCLK falling edge to SDATA three-state
SCLK falling edge to SDATA three-state
Power-up time from full power-down
1, 2
DD
Unit
V min/max
mA typ
mA max
mA typ
μA typ
μA max
μA max
mW max
mW typ
μW typ
μW max
) and timed from a voltage level of 1.6 V.
Test Conditions/Comments
Digital I/Ps = 0 V or V
V
V
V
−40°C to +85°C, typically 0.1 μA
+85°C to +125°C
V
V
V
V
DD
DD
DD
DD
DD
DD
DD
= 3.6 V, SCLK on or off
= 2.35 V to 3.6 V, f
= 3 V
= 3.6 V, f
= 3 V
= 3 V
= 3.6 V, −40°C to +85°C
SAMPLE
= 3 MSPS
DD
SAMPLE
= 3 MSPS