AD7934-6 Analog Devices, AD7934-6 Datasheet
AD7934-6
Specifications of AD7934-6
Related parts for AD7934-6
AD7934-6 Summary of contents
Page 1
... Full shutdown mode: 2 μA maximum 28-lead TSSOP package GENERAL DESCRIPTION The AD7934 12-bit, high speed, low power, successive approximation (SAR) analog-to-digital converter (ADC). The part operates from a single 2 5.25 V power supply and features throughput rates up to 625 kSPS. The part contains a low noise, wide bandwidth, differential track-and-hold amplifier that handles input frequencies MHz ...
Page 2
... ADC Transfer Function............................................................. 15 Typical Connection Diagram ................................................... 16 Analog Input Structure.............................................................. 16 Analog Input Configurations ................................................... 17 Analog Input Selection .............................................................. 19 Reference ..................................................................................... 20 Parallel Interface......................................................................... 21 Power Modes of Operation ....................................................... 24 Power vs. Throughput Rate....................................................... 25 Microprocessor Interfacing....................................................... 25 Application Hints ........................................................................... 27 Grounding and Layout .............................................................. 27 Evaluating the AD7934-6 Performance .................................. 27 Outline Dimensions ....................................................................... 28 Ordering Guide .......................................................................... 28 Rev Page ...
Page 3
... LSB max LSB max V RANGE bit = 0 V RANGE bit = 1 V RANGE bit = 0 V RANGE bit = 1 V typ typ /2, RANGE bit = 0 CM REF RANGE bit = 1 CM REF μA max pF typ When in track pF typ When in hold AD7934-6 ...
Page 4
... AD7934-6 Parameter REFERENCE INPUT/OUTPUT 5 V Input Voltage REF 4 DC Leakage Current V Output Voltage REFOUT V Temperature Coefficient REFOUT V Noise REF V Output Impedance REF V Input Capacitance REF LOGIC INPUTS Input High Voltage, V INH Input Low Voltage, V INL Input Current Input Capacitance ...
Page 5
... CLKIN low pulse width CLKIN high pulse width = (10 RISE FALL , quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the 14 Rev Page AD7934 MHz 625 kSPS, SAMPLE ) and timed from a voltage level of DD ...
Page 6
... AD7934-6 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 4. Parameter V to AGND/DGND AGND/DGND DRIVE Analog Input Voltage to AGND Digital Input Voltage to DGND DRIVE DD Digital Output Voltage to DGND V to AGND REFIN AGND to DGND Input Current to Any Pin Except Supplies ...
Page 7
... CS, RD, and WR. When W/B is low, this pin acts as the high byte enable pin. When HBEN is low, the low byte of data written to or read from the AD7934 DB0 to DB7. When HBEN is high, the top four bits of the data being written to or read from the AD7934-6 are on DB0 to DB3. When reading from the device, DB4 and DB5 of the high byte contain the ID of the channel corresponding to the conversion result (see the channel address bits in Table 9) ...
Page 8
... AGND Analog Ground. This is the ground reference point for all analog circuitry on the AD7934-6. All analog input signals and any external reference signal should be referred to this AGND voltage. The AGND and DGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. ...
Page 9
... CODE Figure 7. Typical DNL @ 1 0.8 DIFFERENTIAL MODE 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 500 1000 1500 2000 2500 3000 CODE Figure 8. Typical INL @ AD7934-6 = 625kSPS 3500 4000 3500 4000 ...
Page 10
... AD7934-6 4 SINGLE-ENDED MODE POSITIVE DNL 0 NEGATIVE DNL –1 0.25 0.50 0.75 1.00 1.25 1.50 V (V) REF Figure 9. DNL vs. V for V REF DIFFERENTIAL MODE 10 SINGLE-ENDED MODE SINGLE-ENDED MODE DIFFERENTIAL MODE 0.5 1.0 1.5 2.0 V (V) REF Figure 10. ENOB vs –0.5 DD –1 –1.5 DD –2.0 –2.5 – ...
Page 11
... It is the deviation of the first REF + 1 LSB) after the zero-code error has been REF , while the signal amplitude × V REF supply of frequency the ADC output the ADC output. S AD7934-6 to REF . See Figure 4. REF . The frequency S and V of IN− ...
Page 12
... The AD7934-6 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves, while the third-order terms are usually at a frequency close to the input frequencies ...
Page 13
... RANGE Selects the analog input range of the AD7934-6. If set to 0, the analog input range extends from set to 1, the analog input range extends from × 2.5 V reference is used; otherwise, care must be taken to ensure that the analog input remains within the supply rails ...
Page 14
... ADD1 and ADD0, in each prior write operation. This mode of operation reflects the normal operation of a multichannel ADC, without the sequencer function being used, where each write to the AD7934-6 selects the next channel for conversion Not used ...
Page 15
... An on-chip channel sequencer allows the user to select a consecutive sequence of channels through which the ADC can cycle with each falling edge of CONVST . The analog input range for the AD7934 × depending on the status of the RANGE bit in the REF control register ...
Page 16
... Figure 17. Ideal Transfer Characteristic with Twos Complement Output Coding and TYPICAL CONNECTION DIAGRAM Figure 18 shows a typical connection diagram for the AD7934-6. The AGND and DGND pins are connected together at the device for good noise suppression. The V /V pin is decoupled to AGND with a 0.47 μF ...
Page 17
... V being preconditioned before it is applied to the AD7934-6. In cases where the analog input amplitude is ±2.5 V, the 3R resistor can be replaced with a resistor of value R. The resultant voltage on the analog input of the AD7934 signal ranging from this case, the 2 × +1.25V 0V – ...
Page 18
... Using an Op Amp Pair An op amp pair can be used to directly couple a differential signal to one of the analog input pairs of the AD7934-6. The circuit configurations in Figure 27 and Figure 28 show how a dual op amp can be used to convert a single-ended signal into a ...
Page 19
... Figure 28. Dual Op Amp Circuit to Convert a Single-Ended Unipolar Signal into a Differential Signal Another method of driving the AD7934 use the differential amplifier. The AD8138 can be used as a single- ended-to-differential amplifier differential-to-differential amplifier. The device is as easy to use amp and greatly simplifies differential signal amplification and driving ...
Page 20
... V ADC to easily interface and 5 V processors. For example the AD7934-6 is operated with a V pin is powered from supply, the AD7934-6 has better dynamic performance with a V interface processors. Care should be taken to ensure , DD ...
Page 21
... DB0 TO DB11 WITH CS AND RD TIED LOW DB0 TO DB11 Figure 34. AD7934-6 Parallel Interface—Conversion and Read Cycle Timing in Word Mode ( the end of the conversion, BUSY goes low and can be used to activate an interrupt service routine. The CS and RD lines are then activated in parallel to read the 12 bits of conversion data. ...
Page 22
... HBEN/DB8 CS RD DB0 TO DB7 Figure 35. AD7934-6 Parallel Interface—Read Cycle Timing for Byte Mode Operation ( The CS and RD signals are gated internally and the level is triggered active low. In either word mode or byte mode, CS and RD can be tied together as the timing specification minimum. This means the bus is constantly driven by the AD7934-6 ...
Page 23
... When operating in word mode, the HBEN input does not exist, and only one write operation is required to write the word of data to the device. Data should be provided on DB0 to DB11. DB0 TO DB11 Figure 36. AD7934-6 Parallel Interface—Write Cycle Timing for Word Mode Operation ( HBEN/DB8 CS WR DB0 TO DB7 Figure 37. AD7934-6 Parallel Interface— ...
Page 24
... The track- and-hold also goes into hold at this point, and remains in hold as long as the device is in shutdown. The AD7934-6 remains in shutdown mode until the next rising edge of CONVST (see Point B in Figure 34 and Figure 38). To keep the device in shutdown for as long as possible, CONVST should idle low between conversions, as shown in Figure 38 ...
Page 25
... A considerable advantage of powering the ADC down after a conversion is that the part’s power consumption is significantly reduced at lower throughput rates. When using the different power modes, the AD7934-6 is only powered up for the duration of the conversion. Therefore, the average power consumption per cycle is significantly reduced. Figure 39 shows a plot of the power vs ...
Page 26
... Parallel interfaces between the AD7934-6 and the TMS32020, TMS320C25, and TMS320C5x family of DSPs are shown in Figure 43. The memory-mapped address chosen for the AD7934-6 should be chosen to fall in the I/O memory space of the DSPs. The parallel interface on the AD7934-6 is fast enough to interface to the TMS32020 with no extra wait states. If high ...
Page 27
... AD7934-6 as possible. Avoid running digital lines under the device as this couples noise onto the die. The analog ground plane should be allowed to run under the AD7934-6 to avoid noise coupling. The power supply lines to the AD7934-6 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line ...
Page 28
... AD7934BRUZ-6 2 −40°C to +85°C 2 AD7934BRUZ-6REEL7 −40°C to +85°C 3 EVAL-AD7934-6CB 4 EVAL-CONTROL-BRD2 1 Linearity error here refers to integral linearity error Pb-free part. 3 This can be used as a standalone evaluation board or in conjunction with the Evaluation Board Controller for evaluation/demonstration purposes. ...