AD7934-6 Analog Devices, AD7934-6 Datasheet - Page 26

• Manufacturer Part Number: AD7934-6
• Description: 4-Channel, 625 kSPS, 12-Bit Parallel ADC with a Sequencer
• Manufacturer: Analog Devices

Specifications of AD7934-6

• Resolution (bits): 12bit
• # Chan: 4
• Sample Rate: 625kSPS
• Interface: Par
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: Uni (Vref),Uni (Vref) x 2
• Adc Architecture: SAR
• Pkg Type: SOP

AD7934-6
AD7934-6 to ADSP-21065L Interface
Figure 42 shows a typical interface between the AD7934-6 and
the
example of one of three DMA handshake modes. The MS
control line is actually three memory select lines. Internal
ADDR
asserted as chip selects. The DMAR
this setup as the interrupt to signal the end of the conversion.
The rest of the interface is a standard handshaking operation.
AD7934-6 to TMS32020, TMS320C25, and
TMS320C5x Interface
Parallel interfaces between the AD7934-6 and the TMS32020,
TMS320C25, and TMS320C5x family of DSPs are shown in
Figure 43. The memory-mapped address chosen for the
AD7934-6 should be chosen to fall in the I/O memory space of
the DSPs. The parallel interface on the AD7934-6 is fast enough
to interface to the TMS32020 with no extra wait states. If high
speed glue logic devices, such as the 74AS, are used to drive the
RD and the WR lines when interfacing to the TMS320C25, no
wait states are necessary. However, if slower logic is used, data
accesses could be slowed sufficiently when reading from, and
writing to, the part to require the insertion of one wait state.
Extra wait states are necessary when using the TMS320C5x at
their fastest clock speeds (see the TMS320C5x User’s Guide for
details).
Data is read from the ADC using the following instruction:
where:
D is the data memory address.
ADC is the AD7934-6 address.
*ADDITIONAL PINS OMITTED FOR CLARITY.
ADDR
ADSP-21065L*
ADSP-21065L
IN D, ADC
0
25 to 24
TO ADDR
D0 TO D31
DMAR
are decoded into MS
MS
WR
RD
23
Figure 42. Interfacing to the ADSP-21065L
X
1
SHARC processor. This interface is an
ADDRESS BUS
ADDRESS
ADDRESS
DECODER
DATA BUS
LATCH
ADDRESS BUS
3 to 0
1
. These lines are then
(DMA request 1) is used in
DSP/USER SYSTEM
CS
BUSY
RD
WR
DB0 TO DB11
AD7934-6*
CONVST
X
Rev. B | Page 26 of 28
*ADDITIONAL PINS OMITTED FOR CLARITY.
AD7934-6 to 80C186 Interface
Figure 44 shows the AD7934-6 interfaced to the 80C186
microprocessor. The 80C186 DMA controller provides two
independent high speed DMA channels where data transfer can
occur between memory and I/O spaces. Each data transfer
consumes two bus cycles, one cycle to fetch data and the other to
store data. After the AD7934-6 has finished a conversion, the
BUSY line generates a DMA request to Channel 1 (DRQ1).
Because of the interrupt, the processor performs a DMA read
operation that also resets the interrupt latch. Sufficient priority
must be assigned to the DMA channel to ensure that the DMA
request is serviced before the completion of the next conversion.
*ADDITIONAL PINS OMITTED FOR CLARITY.
DMD0 TO DMD15
TMS320C25/
TMS320C50*
TMS32020/
80C186*
AD0 TO AD15
Figure 43. Interfacing to the TMS32020/TMS320C25/TMS320C5x
A16 TO A19
A0 TO A15
DRQ1
READY
ALE
WR
STRB
RD
MSC
INT
R/W
IS
X
ADDRESS/DATA BUS
Figure 44. Interfacing to the 80C186
DECODER
ADDRESS
ADDRESS
Q R
EN
ADDRESS BUS
LATCH
S
ADDRESS
DECODER
ADDRESS BUS
DATA BUS
TMS320C25
ONLY
DATA BUS
DSP/USER SYSTEM
CS
WR
RD
BUSY
DB11 TO DB0
MICROPROCESSOR/
AD7934-6*
CS
BUSY
RD
WR
DB0 TO DB11
USER SYSTEM
AD7934-6*
CONVST
CONVST