AD7934-6 Analog Devices, AD7934-6 Datasheet - Page 14

• Manufacturer Part Number: AD7934-6
• Description: 4-Channel, 625 kSPS, 12-Bit Parallel ADC with a Sequencer
• Manufacturer: Analog Devices

Specifications of AD7934-6

• Resolution (bits): 12bit
• # Chan: 4
• Sample Rate: 625kSPS
• Interface: Par
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: Uni (Vref),Uni (Vref) x 2
• Adc Architecture: SAR
• Pkg Type: SOP

AD7934-6
SEQUENCER OPERATION
The configuration of the SEQ0 and SEQ1 bits in the control
register allows the user to use the sequencer function. Table 10
outlines the two sequencer modes of operation.
Writing to the Control Register to Program the Sequencer
The AD7934-6 needs 13 full CLKIN periods to perform a
conversion. If the ADC does not receive the full 13 CLKIN
periods, the conversion aborts. If a conversion is aborted after
Table 10. Sequence Selection Modes
SEQ0
0
0
1
1
SEQ1
0
1
0
1
Sequence Type
This configuration is selected when the sequence function is not used. The analog input channel selected on each
individual conversion is determined by the contents of the channel address bits, ADD1 and ADD0, in each prior write
operation. This mode of operation reflects the normal operation of a multichannel ADC, without the sequencer function
being used, where each write to the AD7934-6 selects the next channel for conversion.
Not used.
Not used.
This configuration is used in conjunction with the channel address bits, ADD1 and ADD0, to program continuous
conversions on a consecutive sequence of channels from Channel 0 to a selected final channel, as determined by the
channel address bits in the control register. When in differential or pseudo differential mode, inverse channels (for
example, V
IN
1, V
IN
0) are not converted in this mode.
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applying 12.5 CLKIN periods to the ADC, ensure that a rising
edge of CONVST or a falling edge of CLKIN is applied to the
part before writing to the control register to program the
sequencer. If these conditions are not met, the sequencer will
not be in the correct state to handle being reprogrammed for
another sequence of conversions and the performance of the
converter is not guaranteed.