AD7934-6 Analog Devices, AD7934-6 Datasheet - Page 15

• Manufacturer Part Number: AD7934-6
• Description: 4-Channel, 625 kSPS, 12-Bit Parallel ADC with a Sequencer
• Manufacturer: Analog Devices

Specifications of AD7934-6

• Resolution (bits): 12bit
• # Chan: 4
• Sample Rate: 625kSPS
• Interface: Par
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: Uni (Vref),Uni (Vref) x 2
• Adc Architecture: SAR
• Pkg Type: SOP

CIRCUIT INFORMATION
The AD7934-6 is a fast, 4-channel, 12-bit, single-supply,
successive approximation analog-to-digital converter.
The part operates from a 2.7 V to 5.25 V power supply
and features throughput rates up to 625 kSPS.
The AD7934-6 provides the user with an on-chip track-and-
hold, an accurate internal reference, an analog-to-digital converter,
and a parallel interface housed in a 28-lead TSSOP package.
The AD7934-6 has four analog input channels that can be
configured to be four single-ended inputs, two fully differential
pairs or two pseudo differential pairs. An on-chip channel
sequencer allows the user to select a consecutive sequence of
channels through which the ADC can cycle with each falling
edge of CONVST .
The analog input range for the AD7934-6 is 0 V to V
to 2 × V
control register. The output coding of the ADC can be either
straight binary or twos complement, depending on the status of
the CODING bit in the control register.
The AD7934-6 provides flexible power management options to
allow users to achieve the best power performance for a given
throughput rate. These options are selected by programming
the power management bits, PM1 and PM0, in the control
register.
CONVERTER OPERATION
The AD7934-6 is a successive approximation ADC based on
two capacitive digital-to-analog converters (DACs). Figure 14
and Figure 15 show simplified schematics of the ADC in
acquisition and conversion phase, respectively. The ADC
comprises control logic, SAR, and two capacitive DACs. Both
figures show the operation of the ADC in differential/pseudo
differential mode. Single-ended mode operation is similar but
V
is closed, SW1 and SW2 are in Position A, the comparator is
held in a balanced condition, and the sampling capacitor arrays
acquire the differential signal on the input.
IN−
V
V
IN+
IN–
is internally tied to AGND. In the acquisition phase, SW3
REF
B
A
A
B
, depending on the status of the RANGE bit in the
V
REF
SW1
SW2
Figure 14. ADC Acquisition Phase
C
C
S
S
SW3
COMPARATOR
CAPACITIVE
CAPACITIVE
CONTROL
LOGIC
DAC
DAC
REF
, or 0 V
Rev. B | Page 15 of 28
When the ADC starts a conversion (see Figure 15), SW3 opens,
and SW1 and SW2 move to Position B, causing the comparator
to become unbalanced. Both inputs are disconnected once the
conversion begins. The control logic and charge redistribution
DACs are used to add and subtract fixed amounts of charge
from the sampling capacitor arrays to bring the comparator
back into a balanced condition. When the comparator is
rebalanced, the conversion is complete. The control logic
generates the output code of the ADC. The output impedances
of the sources driving the V
otherwise, the two inputs have different settling times,
resulting in errors.
ADC TRANSFER FUNCTION
The output coding for the AD7934-6 is either straight binary or
twos complement, depending on the status of the CODING bit
in the control register. The designed code transitions occur at
successive LSB values (that is, 1 LSB, 2 LSBs, and so on), and the
LSB size is V
AD7934-6 for both straight binary and twos complement output
coding are shown in Figure 16 and Figure 17, respectively.
Figure 16. Ideal Transfer Characteristic with Straight Binary Output Coding
V
V
IN+
IN–
111...111
111...110
111...000
011...111
000...010
000...001
000...000
B
A
A
B
REF
V
0V
NOTES
1. V
REF
/4096. The ideal transfer characteristics of the
SW1
SW2
REF
Figure 15. ADC Conversion Phase
1 LSB
C
C
IS EITHER V
S
S
ANALOG INPUT
IN+
SW3
REF
and the V
1 LSB = V
OR 2 × V
COMPARATOR
REF
REF
IN−
/4096
.
pins must match;
+V
REF
AD7934-6
CAPACITIVE
CAPACITIVE
– 1 LSB
CONTROL
LOGIC
DAC
DAC