AD7993 Analog Devices, AD7993 Datasheet - Page 15

• Manufacturer Part Number: AD7993
• Description: 4-Channel, 10-Bit ADC with I2C Compatible Interface in 16-Lead TSSOP
• Manufacturer: Analog Devices

Specifications of AD7993

• Resolution (bits): 10bit
• # Chan: 4
• Sample Rate: 188kSPS
• Interface: I²C/Ser 2-Wire,Ser
• Analog Input Type: SE-Uni
• Ain Range: Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: SOP

CIRCUIT INFORMATION
The AD7993/AD7994 are low power, 10- and 12-bit, single-
supply, 4-channel A/D converters, respectively. The parts can
be operated from a 2.7 V to 5.5 V supply.
The AD7993/AD7994 provide the user with a 4-channel
multiplexer, an on-chip track-and-hold, an A/D converter, an
on-chip oscillator, internal data registers, and an I
serial interface, all housed in a 16-lead TSSOP package that
offers the user considerable space-saving advantages over
alternative solutions. The AD7993/AD7994 require an external
reference in the range of 1.2 V to V
The AD7993/AD7994 normally remain in a power-down state
while not converting. When supplies are first applied, the parts
come up in a power-down state. Power-up is initiated prior to
a conversion, and the device returns to shutdown upon com-
pletion of the conversion. Conversions can be initiated on the
AD7993/AD7994 by pulsing the CONVST signal, using an
automatic cycle interval mode, or using a command mode
where wake-up and a conversion occurs during a write address
function (see the Modes of Operation section). When the con-
version is complete, the AD7993/AD7994 again enter shutdown
mode. This automatic shut-down feature allows power saving
between conversions. Any read or write operations across the
I
CONVERTER OPERATION
The AD7993/AD7994 are successive approximation analog-to-
digital converters based around a capacitive DAC. Figure 18 and
Figure 19 show simplified schematics of an ADC during the
acquisition and conversion phase, respectively. Figure 18 shows
an ADC during the acquisition phase. SW2 is closed and SW1
is in Position A. The comparator is held in a balanced condition
and the sampling capacitor acquires the signal on V
2
AGND
C interface can occur while the devices are in shutdown.
V
IN
A
SW1
B
Figure 18. ADC Acquisition Phase
SW2
DD
.
COMPARATOR
2
C-compatible
CAPACITIVE
IN
CONTROL
x.
LOGIC
DAC
Rev. 0 | Page 15 of 32
When the ADC starts a conversion, as shown in Figure 19, SW2
opens and SW1 moves to Position B, causing the comparator to
become unbalanced. The input is disconnected once the con-
version begins. The control logic and the capacitive DAC are
used to add and subtract fixed amounts of charge from the
sampling capacitor to bring the comparator back into a
balanced condition. When the comparator is rebalanced, the
conversion is complete. The control logic generates the ADC
output code. Figure 20 shows the ADC transfer function.
ADC Transfer Function
The output coding of the AD7993/AD7994 is straight binary.
The designed code transitions occur at successive integer LSB
values—that is, 1 LSB, 2 LSB, and so on. The LSB size is
REF
Figure 20 shows the ideal transfer characteristic for the
AD7993/AD7994.
AGND
V
IN
IN
/1024 for the AD7993 and REF
SW1
111...111
111...110
111...000
011...111
000...010
000...001
000...000
A
Figure 20. AD7993/AD7994 Transfer Characteristic
B
Figure 19. ADC Conversion Phase
AGND + 1LSB
SW2
ANALOG INPUT
0V TO REF
AD7993 1LSB = REF
AD7994 1LSB = REF
IN
COMPARATOR
IN
/4096 for the AD7994.
+REF
AD7993/AD7994
IN
– 1LSB
IN
IN
CAPACITIVE
/1024
/4096
CONTROL
LOGIC
DAC