AD7993 Analog Devices, AD7993 Datasheet - Page 22

• Manufacturer Part Number: AD7993
• Description: 4-Channel, 10-Bit ADC with I2C Compatible Interface in 16-Lead TSSOP
• Manufacturer: Analog Devices

Specifications of AD7993

• Resolution (bits): 10bit
• # Chan: 4
• Sample Rate: 188kSPS
• Interface: I²C/Ser 2-Wire,Ser
• Analog Input Type: SE-Uni
• Ain Range: Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: SOP

AD7993/AD7994
CYCLE TIMER REGISTER
The cycle timer register is an 8-bit read/write register that stores
the conversion interval value for the automatic cycle interval
mode of the AD7993/AD7994 (see the Modes of Operation
section). D5 to D3 of the cycle timer register are unused and
should contain 0s at all times. On power-up, the cycle timer
register contains all 0s, thus disabling automatic cycle operation
of the AD7993/AD7994. To enable automatic cycle mode, the
user must write to the cycle timer register, selecting the required
conversion interval. Table 24 shows the structure of the cycle
timer register while Table 25 shows how the bits in this register
are decoded to provide various automatic sampling intervals.
Table 24. Cycle Timer Register and Default Power-Up Settings
D7
Sample
Delay
0
Table 25. Cycle Timer Intervals
D2
0
0
0
0
1
1
1
1
D1
0
0
1
1
0
0
1
1
D6
Bit Trial
Delay
0
D0
0
1
0
1
0
1
0
1
Typical Conversion Interval
(T
Mode not selected
T
T
T
T
T
T
T
CONVERT
CONVERT
CONVERT
CONVERT
CONVERT
CONVERT
CONVERT
CONVERT
D5
0
0
× 32
× 64
× 128
× 256
× 512
× 1024
× 2048
= conversion time of the ADC)
D4
0
0
D3
0
0
D2
Cyc
Bit2
0
D1
Cyc
Bit1
0
D0
Cyc
Bit0
0
Rev. 0 | Page 22 of 32
SAMPLE DELAY AND BIT TRIAL DELAY
It is recommended that no I
conversion is taking place. However, if this is not possible, for
example when operating in Mode 2 or Mode 3, then in order to
maintain the performance of the ADC, Bits D7 and D6 in the
cycle timer register are used to delay critical sample intervals
and bit trials from occurring while there is activity on the I
bus. This results in a quiet period for each bit decision. In
certain cases where there is excessive activity on the interface
lines, this may have the effect of increasing the overall
conversion time. However, if bit trial delays extend longer than
1 µs, the conversion terminates.
When Bits D7 and D6 are both 0, the bit trial and sample
interval delaying mechanism is implemented. The default
setting of D7 and D6 is 0. To turn off both delay mechanisms,
set D7 and D6 to 1.
Table 26. Cycle Timer Register and Defaults at Power-Up
D7
Sample
Delay
0
D6
Bit Trial
Delay
0
D5
0
0
2
C bus activity occur when a
D4
0
0
D3
0
0
D2
Cyc
Bit 2
0
D1
Cyc
Bit 1
0
D0
Cyc
Bit 0
0
2
C