AD7993 Analog Devices, AD7993 Datasheet - Page 20

• Manufacturer Part Number: AD7993
• Description: 4-Channel, 10-Bit ADC with I2C Compatible Interface in 16-Lead TSSOP
• Manufacturer: Analog Devices

Specifications of AD7993

• Resolution (bits): 10bit
• # Chan: 4
• Sample Rate: 188kSPS
• Interface: I²C/Ser 2-Wire,Ser
• Analog Input Type: SE-Uni
• Ain Range: Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: SOP

AD7993/AD7994
CONVERSION RESULT REGISTER
The conversion result register is a 16-bit read-only register that
stores the conversion result from the ADC in straight binary
format. A 2-byte read is necessary to read data from this
register. Table 13 shows the contents of the first byte to be read
from the AD7993/AD7994 and Table 14 shows the contents of
the second byte to be read.
Table 13. Conversion Value Register (First Read)
D15
Alert_Flag
Table 14. Conversion Value Register (Second Read)
D7
B7
The conversion result of the AD7993/AD7994 consists of an
Alert_Flag bit, a zero bit, two channel identifier bits, and the
10- and 12-bit data result. For the AD7993, the 2 LSB (D1 and
D0) of the second read contain two trailing 0s.
The Alert_Flag bit indicates whether the conversion result
being read or any other channel result has violated the limit
registers associated with it. If an alert occurs, the master may
wish to read the alert status register to obtain more information
on where the alert occurred if the Alert_Flag bit is set.
The Alert_Flag bit is followed by a zero bit and two channel
identifier bits that indicate which channel the conversion result
corresponds to. These, in turn, are followed by the 10- bit and
12-bit conversion result, MSB first.
Table 15. Channel Identifier Bits
Alert_Flag
0/1
0/1
0/1
0/1
LIMIT REGISTERS
The AD7993/AD7994 have four pairs of limit registers. Each
pair stores high and low conversion limits for each analog
input channel. Each pair of limit registers has one associated
hysteresis register. All 12 registers are 16 bits wide; only the
12 LSBs of the registers are used for the AD7993/AD7994. For
the AD7993, the 2 LSBs, D1 and D0, should contain 0s. On
power-up, the contents of the DATA
channel is full scale, while the contents of the DATA
registers is zero scale by default. The AD7993/AD7994 signal
an alert (in either hardware, software, or both, depending on
configuration) if the conversion result moves outside the upper
or lower limit set by the limit registers.
D6
B6
D14
Zero
Zero
0
0
0
0
D5
B5
D13
CH
CH
0
0
1
1
ID1
D4
B4
ID1
D12
CH
CH
0
1
0
1
ID0
D3
B3
ID0
HIGH
D11
MSB
register for each
Channel 1 (V
Channel 2 (V
Channel 3 (V
Channel 4 (V
D2
B2
Channel No. Result
D10
B10
D1
B1/0
LOW
IN
IN
IN
IN
D9
B9
1)
2)
3)
4)
D0
B0/0
Rev. 0 | Page 20 of 32
D8
B8
DATA
The DATA
registers; only the 12 LSBs of each register are used. This
register stores the upper limit that activates the alert output
and/or the Alert_Flag bit in the conversion result register. If the
value in the conversion result register for a channel is greater
than the value in the DATA
alert occurs. When the conversion result returns to a value at
least N LSB below the DATA
output pin and Alert_Flag bit are reset. The value of N is taken
from the hysteresis register associated with that channel. The
ALERT pin can also be reset by writing to Bits D2 and D1 in the
configuration register. For the AD7993, D1 and D0 of the
DATA
Table 16. DATA
D15
0
Table 17. DATA
D7
B7
DATA
The DATA
register; only the 12 LSBs of each register are used. The register
stores the lower limit that activates the ALERT output and/or
the Alert_Flag bit in the conversion result register. If the value
in the conversion result register for a channel is less than the
value in the DATA
occurs. When the conversion result returns to a value at least N
LSB above the DATA
and Alert_Flag bit are reset. The value of N is taken from the
hysteresis register associated with that channel. The ALERT
output pin can also be reset by writing to Bits D2 and D1 in the
configuration register. For the AD7993, D1 to D0 of the
DATA
Table 18. DATA
D15
0
Table 19. DATA
D7
B7
HIGH
HIGH
LOW
LOW
D14
0
D6
B6
D14
0
D6
B6
Register CH1/CH2/CH3/CH4
register should contain 0s.
Register CH1/CH2/CH3/CH4
register should contain 0s.
HIGH
LOW
register for each channel is a 16-bit read/write
registers for each channel are 16-bit read/write
D13
0
D5
B5
D13
0
D5
B5
HIGH
HIGH
LOW
LOW
LOW
LOW
Register (First Read/Write)
Register (Second Read/Write)
Register (First Read/Write)
Register (Second Read/Write)
register for that channel, an ALERT
register value, the ALERT output pin
D12
0
D4
D12
0
D4
B4
B4
HIGH
HIGH
register for that channel, an
register value, the ALERT
D11
B11
D3
B3
D11
B11
D3
B3
D10
B10
D2
B2
D10
B10
D2
B2
D9
B9
D1
B1
D9
B9
D1
B1
D8
B8
D0
B0
D8
B8
D0
B0