AD7787 Analog Devices, AD7787 Datasheet
AD7787
Specifications of AD7787
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AD7787 Summary of contents
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... Weigh scales loops GENERAL DESCRIPTION The AD7787 is a low power, complete analog front end for low frequency measurement applications. It contains a low noise 24-bit Σ-Δ ADC with one differential input and one single- ended input that can be buffered or unbuffered. ...
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... AD7787 TABLE OF CONTENTS Specifications..................................................................................... 3 Timing Characteristics..................................................................... 5 Absolute Maximum Ratings............................................................ 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Typical Performance Characteristics ............................................. 9 On-Chip Registers .......................................................................... 10 Communications Register (RS1, RS0 = 0, 0)........................... 10 Status Register (RS1, RS0 = 0, 0; Power-On/Reset = 0×8C)........................................................................................ 11 Mode Register (RS1, RS0 = 0, 1; Power-On/Reset = 0× ...
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... Hz, FS[2:0] = 101 . 90 dB typ, 60 ± 1 Hz, FS[2:0] = 011 4 . AIN = 1 V. 100 dB typ ± (FS[2:0] = 101 ), 60 ± (FS[2:0] = 011 73 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[2:0] = 100 typ, 50 ± 1 Hz, FS[2:0] = 101 . typ, 60 ± 1 Hz, FS[2:0] = 011 . AD7787 to MIN ...
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... Full-scale error applies to both positive and negative full scale and applies at the factory calibration conditions (V 3 The AD7787 can tolerate absolute analog input voltages down to GND − 200 mV but the leakage current will increase. 4 FS[2:0] are the three bits used in the filter register to select the output word rate. ...
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... CS Falling Edge to SCLK Active Edge Setup Time ns min Data Valid to SCLK Edge Setup Time ns min Data Valid to SCLK Edge Hold Time ns min CS Rising Edge to SCLK Edge Hold Time Rev Page AD7787 = (10 and timed unless otherwise noted. ...
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... AD7787 DOUT/RDY (O) SCLK (I) I (1.6mA WITH V SINK 100µA WITH OUTPUT 1.6V PIN 50pF I (200µA WITH V SOURCE 100µA WITH V DD Figure 2. Load Circuit for Timing Characterization CS ( MSB SCLK ( INPUT OUTPUT Figure 3. Read Cycle Timing Diagram ...
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... DD of this specification is not implied. Exposure to absolute −0 0 maximum rating conditions for extended periods may affect −40°C to +105°C device reliability. −65°C to +150°C 150°C 206°C/W 44°C/W 300°C 220°C Rev Page AD7787 ...
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... Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control registers 10 DIN within the ADC; the register selection bits of the communications register identifying the appropriate register. SCLK DIN DOUT/RDY 2 9 AD7787 AIN1(+) TOP VIEW DD (Not to Scale) AIN1(–) GND 4 7 ...
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... UPDATE RATE T = 25°C A RMS NOISE = 1.25µF CODE 2.048V DD REF 1.1875Hz UPDATE RATE T = 25°C, RMS NOISE = 1.25µ READ NO UPDATE RATE = 16.6Hz T = 25°C A 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 V (V) REF Figure 11. RMS Noise vs. Reference Voltage AD7787 8388616 100 4.5 5.0 ...
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... AD7787 ON-CHIP REGISTERS The ADC is controlled and configured via a number of on-chip registers, which are described on the following pages. In the following descriptions, set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise noted. COMMUNICATIONS REGISTER (RS1, RS0 = 0, 0) The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the communications register ...
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... SR1 to CH1 to These bits indicate which channel is being converted by the ADC. SR0 CH0 Channel AIN1(+) − AIN1(−) AIN2 AIN1(−) − AIN1(−) V Monitor DD SR5 SR4 SR3 0 (0) 0 (0) 1 (1) Rev Page SR2 SR1 SR0 1 (1) CH1 (0) CH0 (0) AD7787 ...
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... MR1 BUF Configures the AD7787 for buffered or unbuffered mode of operation. If cleared, the ADC operates in unbuffered mode, lowering the power consumption of the device. If set, the device operates in buffered mode, allowing the user to place source impedances on the front end without contributing gain errors to the system. ...
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... These bits must be programmed with a Logic 0 for correct operation. FR6 FR5 to CLKDIV1 These bits are used to operate the AD7787 in the lower power modes. The clock is internally divided and the FR4 to CDIV0 power is reduced. In the low power modes, the update rates will scale with the clock frequency so that dividing the clock by 2 causes the update rate to be reduced by a factor of 2 also ...
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... When the internal clock is reduced, the update rate is also reduced. For example, if the filter bits are set to give an update rate of 16.6 Hz when the AD7787 is operated in full power mode, the update rate equals 8 divide-by-2 mode. In the low power modes, there may be some degradation in the ADC performance. Typ Current, Unbuffered (µ ...
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... The serial interface can be reset by writing a series the DIN input Logic 1 is written to the AD7787 line for at least 32 serial clock cycles, the serial interface is reset. In 3-wire systems, this ensures that the interface can be reset to a known state if the interface gets lost due to a software error or some glitch in the system ...
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... MD1 to 1 and MD0 the mode register, the AD7787 powers up, performs a single conversion, and then returns to shutdown mode. When a single conversion is initiated, the AD7787’s oscillator requires power up and settle. The AD7787 then performs a conversion which requires 2 × t ...
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... Continuous Read Mode Rather than write to the communications register each time a conversion is complete to access the data, the AD7787 can be placed in continuous read mode. By writing 00111100 (Channel AIN1) or 00111101 (Channel AIN2) to the communications register, the user only needs to apply the appropriate number of SCLK cycles to the ADC, and the 24-bit word is automatically placed on the DOUT/ RDY line when a conversion is complete ...
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... REFERENCE INPUT The AD7787 has a single-ended reference that is 2.5 V nominal, − 100 mV. Care DD but the AD7787 is functional with reference voltages from 0 for the transducer on the analog input also drives the reference voltage for the part, the effect of the low frequency noise in the ...
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... AD7787 is more immune to noise interference than a conventional high resolution converter. However, because the resolution of the AD7787 is so high, and the noise levels from the AD7787 are so low, care must be taken with regard to grounding and layout. The printed circuit board that houses the AD7787 should be designed such that the analog and digital sections are separated and confined to certain areas of the board ...
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... AD7787 OUTLINE DIMENSIONS ORDERING GUIDE Models Temperature Range AD7787BRM −40°C to +105°C AD7787BRM-REEL −40°C to +105°C EVAL-AD7787EB © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 3.00 BSC 10 6 4.90 BSC 3.00 BSC 1 ...