AD7787 Analog Devices, AD7787 Datasheet - Page 12

• Manufacturer Part Number: AD7787
• Description: Low Power, 2-Channel 24-Bit Sigma-Delta ADC
• Manufacturer: Analog Devices

Specifications of AD7787

• Resolution (bits): 24bit
• # Chan: 2
• Sample Rate: n/a
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni,SE-Bip,SE-Uni
• Ain Range: (2Vref) p-p,(Vref) p-p,Uni (Vref)
• Adc Architecture: Sigma-Delta
• Pkg Type: SOP

AD7787
MODE REGISTER (RS1, RS0 = 0, 1; POWER-ON/RESET = 0×02)
The mode register is an 8-bit register from which data can be read or to which data can be written. This register is used to configure the
ADC for unipolar or bipolar mode, to enable or disable the buffer, or to place the device into power-down mode. Table 9 outlines the bit
designations for the mode register. MR0 through MR7 indicate the bit locations, MR denoting the bits are in the mode register. MR7
denotes the first bit of the data stream. The number in the parenthesis indicates the power-on/reset default status of that bit. Any write to
the setup register resets the modulator and filter and sets the RDY bit.
MR7
MD1 (0)
Table 9. Mode Register Bit Designations
Bit
Location
MR7 to
MR6
MR5 to
MR4
MR3
MR2
MR1
MR0
Table 10. Operating Modes
MD1
0
0
1
1
Bit
Name
MD1 to
MD0
0
BO
U/B
BUF
0
MR6
MD0 (0)
Description
Mode Select Bits. These bits select between continuous conversion mode, single conversion mode, and standby
mode. In continuous conversion mode, the ADC continuously performs conversions and places the result in the
data register. RDY goes low when a conversion is complete. The user can read these conversions by placing the
device in continuous read mode whereby the conversions are automatically placed on the DOUT line when SCLK
pulses are applied. Alternatively, the user can instruct the ADC to output the conversion by writing to the
communications register. After power-on, the first conversion is available after a period 2/f
conversions are available at a frequency of f
when conversions are not being performed. When single conversion mode is selected, the ADC powers up and
performs a single conversion, which occurs after a period 2/f
RDY goes low, and the ADC returns to power-down mode. The conversion remains in the data register and RDY
remains active (low) until the data is read or another conversion is performed (see Table 10).
These bits must be programmed with a Logic 0 for correct operation.
Burnout Current Enable Bit. When this bit is set to 1 by the user, the 100 nA current sources in the signal path are
enabled. When BO = 0, the burnout currents are disabled. The burnout currents can be enabled only when the
buffer is active.
Unipolar/Bipolar Bit. Set by user to enable unipolar coding, i.e., zero differential input results in 0x000000 output
and a full-scale differential input results in 0xFFFFFF output. Cleared by the user to enable bipolar coding. Negative
full-scale differential input results in an output code of 0x000000, zero differential input results in an output code of
0x800000, and a positive full-scale differential input will result in an output code of 0xFFFFFF.
Configures the AD7787 for buffered or unbuffered mode of operation. If cleared, the ADC operates in unbuffered
mode, lowering the power consumption of the device. If set, the device operates in buffered mode, allowing the
user to place source impedances on the front end without contributing gain errors to the system.
This bit must be programmed with a Logic 0 for correct operation.
MD0
0
1
0
1
MR5
0 (0)
Mode
Continuous Conversion Mode (Default)
Reserved
Single Conversion Mode
Power-Down Mode
MR4
0 (0)
Rev. 0 | Page 12 of 20
ADC
. In single conversion mode, the ADC is placed in power-down mode
MR3
BO (0)
ADC
. The conversion result is placed in the data register,
MR2
U/B (0)
MR1
BUF (1)
ADC
while subsequent
MR0
0 (0)