AD7787 Analog Devices, AD7787 Datasheet - Page 5

• Manufacturer Part Number: AD7787
• Description: Low Power, 2-Channel 24-Bit Sigma-Delta ADC
• Manufacturer: Analog Devices

Specifications of AD7787

• Resolution (bits): 24bit
• # Chan: 2
• Sample Rate: n/a
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni,SE-Bip,SE-Uni
• Ain Range: (2Vref) p-p,(Vref) p-p,Uni (Vref)
• Adc Architecture: Sigma-Delta
• Pkg Type: SOP

TIMING CHARACTERISTICS
Sample tested during initial release to ensure compliance. All input signals are specified with t
from a voltage level of 1.6 V (see Figure 3 and Figure 4).
V
Table 2.
Parameter
t
t
Read Operation
t
t
t
t
t
Write Operation
t
t
t
t
1
2
3
4
3
4
1
2
5
6
7
8
9
10
11
These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the V
The SCLK active edge is the falling edge of SCLK.
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and, as such, are independent of external bus loading capacitances.
RDY returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high,
although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read
only once.
1
3, 4
DD
= 2.5 V to 5.25 V; GND = 0 V, REFIN = 2.5 V, CDIV1 = CDIV0 = 0, Input Logic 0 = 0 V, Input Logic 1 = V
Limit at T
100
100
0
60
80
0
60
80
10
80
100
10
0
30
25
0
MIN
, T
MAX
(B Version)
Rev. 0 | Page 5 of 20
Unit
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns max
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns min
Conditions/Comments
SCLK High Pulse Width
SCLK Low Pulse Width
CS Falling Edge to DOUT/RDY Active Time
V
V
SCLK Active Edge to Data Valid Delay
V
V
Bus Relinquish Time after CS Inactive Edge
SCLK Inactive Edge to CS Inactive Edge
SCLK Inactive Edge to DOUT/RDY High
CS Falling Edge to SCLK Active Edge Setup Time
CS Rising Edge to SCLK Edge Hold Time
Data Valid to SCLK Edge Setup Time
Data Valid to SCLK Edge Hold Time
DD
DD
DD
DD
= 4.75 V to 5.25 V
= 2.5 V to 3.6 V
= 4.75 V to 5.25 V
= 2.5 V to 3.6 V
R
= t
F
= 5 ns (10% to 90% of V
OL
or V
OH
limits.
DD
, unless otherwise noted.
2
DD
2
) and timed
AD7787