AD9863 Analog Devices, AD9863 Datasheet
AD9863
Specifications of AD9863
Available stocks
Related parts for AD9863
AD9863 Summary of contents
Page 1
... AD9863 and the device to which it connects. The AD9863 can use either mode pins or a serial programma- ble interface (SPI) to configure the interface bus, operate the ADC in a low power mode, configure the TxDAC interpolation rate, and control ADC and TxDAC power-down ...
Page 2
... AD9863 TABLE OF CONTENTS Tx Path Specifications...................................................................... 3 Rx Path Specifications...................................................................... 4 Power Specifications......................................................................... 5 Digital Specifications........................................................................ 5 Timing Specifications....................................................................... 6 Absolute Maximum Ratings............................................................ 7 Thermal Resistance ...................................................................... 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Typical Performance Characteristics ........................................... 10 REVISION HISTORY 4/05—Rev Rev. A Changes to Ordering Guide .......................................................... 40 11/03— Revision 0: Initial Version Terminology ...
Page 3
... Full V Full V Full IV Full IV Full IV Full IV Full IV TxDAC 50Ω 50Ω Figure 2. Diagram Showing Termination of 100 Ω Differential Load for Some TxDAC Measurements Rev Page AD9863 1 ; TxPGA = 20 dB; AVDD = DVDD = 3.3 V, Min Typ Max Unit 12 Bits 200 MHz +3 −3.5 +0 −0.1 1 ...
Page 4
... Input Capacitance Input Bandwidth Differential Analog Input Voltage Range Rx PATH DC ACCURACY Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Aperture Delay Aperture Uncertainty (Jitter) Input Referred Noise AD9863 Rx PATH DYNAMIC PERFORMANCE (V = –0.5 dBFS MHz SNR SINAD THD (Second to Ninth Harmonics) SFDR, Wide Band (DC to Nyquist) ...
Page 5
... Min Typ Max IV 2.7 3.6 IV 2.7 3.6 IV 2.7 3 103 Min Typ Max Unit V DRVDD − 0.7 0.4 V DRVDD − 0 µ Input clock cycles 2 AD9863 Unit ...
Page 6
... AD9863 TIMING SPECIFICATIONS Table 5. Parameter INPUT CLOCK CLKIN2 Clock Rate (PLL Bypassed) PLL Input Frequency PLL Ouput Frequency TxPATH DATA Setup Time (HD24 Mode, Time Required Before Data Latching Edge) Hold Time (HD24 Mode, Time Required After Data Latching Edge) Latency 1× Interpolation (Data In Until Peak Output Response) Latency 2× ...
Page 7
... THERMAL RESISTANCE 300°C 64-lead LFCSP (4-layer board): θ = 24.2 (paddle soldered to ground plan, 0 LPM air) JA −65°C to +150°C θ = 30.8 (paddle not soldered to ground plan, 0 LPM air) JA Rev Page AD9863 ...
Page 8
... U11 IFACE1 L11 RESET 47 CLKIN2 48 CLKIN1 SPI_DIO 1 SPI_CLK 2 SPI_SDO 3 4 DVDD 5 DVSS 6 AD9863 AVDD 7 IOUT–A TOP VIEW 8 (Not to Scale) IOUT+A 9 AGND 10 REFIO 11 FSADJ 12 AGND 13 IOUT+B 14 IOUT–B 15 AVDD Figure 3 ...
Page 9
... ADC Band Gap Reference. ADC A Differential Input. ADC Top Reference. Rx Analog Power-Down Control. Tx Analog Power-Down Control. SPI: Serial Port Chip Select. At power-up or reset, this must be high. No SPI: Tie low to disable SPI and use mode pins. This pin must be tied low. Rev Page AD9863 ...
Page 10
... Figure 7. AD9863 Rx Path Dual-Tone FFT of Rx Channel A Path 0 –10 –20 –30 40 –50 –60 –70 –80 –90 –100 –110 Figure 8. AD9863 Rx Path Dual-Tone FFT of Rx Channel A Path 0 –10 –20 –30 40 –50 –60 –70 –80 –90 –100 –110 Figure 9. AD9863 Rx Path Dual-Tone FFT of Rx Channel A Path Rev ...
Page 11
... Figure 13. AD9863 Rx Path Dual-Tone FFT of Rx Channel A Path NORMAL POWER @ 50MSPS Figure 14. AD9863 Rx Path at 50 MSPS, 10 MHz Input Tone –50 –55 –60 –65 NORMAL POWER @ 50MSPS –70 –75 ULTRALOW POWER @ 16MSPS – Figure 15. AD9863 Rx Path at 50 MSPS, 10 MHz Input Tone Rev ...
Page 12
... THD 0 –5 –10 –15 –20 –25 –30 INPUT AMPLITUDE (dBFS) Figure 19. AD9863 Rx Path at 50 MSPS, 10 MHz Input Tone THD and SFDR Performance vs. Input Amplitude AVE +85°C AVE +25°C AVE –40°C 2.7 3.0 3.3 INPUT FREQUENCY (MHz) Figure 20. AD9863 Rx Path at 50 MSPS, 10 MHz Input Tone SINAD Performance vs ...
Page 13
... OUTPUT FREQUENCY (MHz) Figure 24. AD9863 Tx Path THD vs. Output Frequency of Tx Channel A –10 –20 –30 40 –50 –60 –70 –80 –90 –100 –110 20 25 Figure 25. AD9863 Tx Path 5 MHz Single-Tone Output FFT of Tx Channel 100 Figure 26. AD9863 Tx Path SINAD/SNR vs. Output Frequency of Tx Path – ...
Page 14
... OFDM Signal in Figure 28 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 FREQUENCY (MHz) Figure 30. AD9863 Tx Path FFT of OFDM Signal in Figure 28 with 1x Interpolation –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 27.5 32.5 –20 –30 –40 –50 – ...
Page 15
... Figure 35. AD9863 Tx Path FFT, Lower-Band IMD Products of OFDM Signal in Figure 34 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 FREQUENCY (MHz) Figure 36. AD9863 Tx Path FFT of OFDM Signal in Figure 34, with 1× Interpolation –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 7.4 7.6 7.8 8.0 –30 – ...
Page 16
... FREQUENCY (MHz) Figure 44. AD9863 Tx Path FFT, Upper-Band IMD Products of OFDM Signal in Figure 40 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 FREQUENCY (MHz) Figure 45. AD9863 Tx Path FFT of OFDM Signal in Figure 40, with 2× Interpolation 7.02 7.03 35.1 35.3 35 ...
Page 17
... SFDR does not include harmonic ⎞ distortion components. Z − ⎟ RMS INPUT ⎟ 001 ⎠ Worst Other Spur The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonics) reported in dBc. Rev Page AD9863 ...
Page 18
... ADC modes, TxDAC power scaling, and a half-duplex mode, which automatically disables the unused digital path. The AD9863 uses two 12-bit buses to transfer Rx path data and Tx path data. These two buses support 24-bit parallel data transfers or 12-bit interleaved data transfers. The bus is configurable through either external mode pins or internal registers settings ...
Page 19
... In systems that must use dc coupling, use an op amp to comply with the input requirements of the AD9863. The inputs accept a signal with p-p differential input swing centered about one-half of the supply voltage (AVDD/2). If the dc bias is supplied exter- ...
Page 20
... Figure 49 shows the typical analog power dissipation (ADC_AVDD = 3.3 V) for the ADC vs. sampling rate for the normal power, low power, and ultralow power modes. ), Either of the ADCs in the AD9863 Rx path can be placed in INPUT standby mode independently by writing to the appropriate SPI register bits in Register 3, Register 4, and Register 5. The ...
Page 21
... In addition, a sleep mode is available that turns off the DAC output current but leaves all other circuits active for a modest power savings. An SPI-compliant serial port is used to program the many features of the AD9863. Note that in power-down mode, the SPI port is still active. DAC Equivalent Circuits The AD9863 Tx path, consisting of dual 12-bit DACs, is shown in Figure 50 ...
Page 22
... MHz, but optimal phase noise with respect to VCO speed is achieved by running it in the range of 64 MHz to 200 MHz. Power Dissipation The AD9863 Tx path power is derived from three voltage supplies: AVDD, DVDD, and DRVDD. IDRVDD and IDVDD are very dependent on the input data rate, the interpolation rate, and the activation of the internal digital modulator ...
Page 23
... DIGITAL BLOCK The AD9863 digital block allows the device to be configured in various timing and operation modes. The following sec- tions discuss the flexible I/O interfaces, the clock distribution block, and the programming of the device through mode pins or SPI registers. Table 10. Flexible Data Interface Modes ...
Page 24
... Low) 1 Clone mode not available without SPI. Table 12 describes AD9863 pin function (when SPI programming is used) relative to flexible I/O mode and for half-duplex modes, whether transmitting or receiving. Table 12. AD9863 Pin Function vs. Interface Mode (Configured through the SPI Registers) Mode Name U12 Bus ...
Page 25
... Rx and Tx synchronization pins (RxSYNC and TxSYNC). Both the U12 and L12 buses are used on the AD9863, but the logic level of the Tx/ Rx selector (controlled through IFACE1 pin) is used to disable and three-state the unused bus, allowing U12 and L12 to be tied together ...
Page 26
... The flexible interface can be configured with or without the SPI, although more options and flexibility are available when using the SPI to program the AD9863. Mode pins can be used to power down sections of the device, reduce overall power consumption, configure the flexible I/O interface, and program the interpolation setting ...
Page 27
... Logic high disables the DAC clocks and disables some bias circuitry to reduce power consumption. Tx/Rx Power-Down Control. Tx/Rx pin enables the appropriate path in the half-duplex mode. Logic low disables the Tx path and enables the Rx path. Logic high disables the Rx path and enables the Tx path. Rev Page AD9863 ...
Page 28
... The flexible interface can be configured with register settings. Using the register allows more device programmability. Table 15 shows the required register writes to configure the AD9863 for FD, optional FD, HD24, optional HD24, HD12, optional HD12, and clone modes. Note that for modes that use interleaved data buses, enabling 2× or 4× interpolation is required. ...
Page 29
... SPI Register Map Registers 0x00 to 0x29 of the AD9863 provide flexible operation of the device. The SPI allows access to many configurable options. Detailed descriptions of the bit functions are found in Table 17. Table 16. Register Map Reg. Reg. Name Add 7 6 General 0x00 SDIO BiDir LSB first ...
Page 30
... Setting this register bit high forces the CLKIN2 PLL multiplier to a power-down state. This mode can be used to conserve power or to bypass the internal PLL. To operate the AD9863 when the PLL is bypassed, CLKIN2 must be supplied with a clock equal to the fastest Tx path clock. ...
Page 31
... The TxPGA gain is controlled through register TxPGA gain setting and, by default, is updated immediately after the register write. If this bit is set, the TxPGA gain update is synchronized with the falling edge of a signal applied to the TxPwrDwn pin and is enabled during the wake-up from power-down. Rev Page AD9863 ...
Page 32
... AD9863 Register Bit Bit 4: TxPGA Fast Update (Mode) Register 0x13: I/O Configuration Bit 7: Tx Twos Complement Bit 6: Rx Twos Complement Bit 5: Tx Inverse Sample Bit 1, Bit 0: Interpolation Control Register 0x14: I/O Configuration Bit 5: Dig Loop On Bit 4: SPIFD/HD Bit 3: SpiTx/ Rx Bit 2: SpiB12/24 Bit 1: SPI IO Control ...
Page 33
... CPU overhead when register access requires only one byte. An example of this is to write the AD9863 power-down bits. All data input to the AD9863 is registered on the rising edge of SCLK. All data is driven out of the AD9863 on the falling edge of SCLK. ...
Page 34
... AD9863 Write Operations The SPI write operation uses the instruction header to config- ure a 1-byte or 2-byte register write using the 2/ 1 byte setting. The instruction byte followed by the register data is written serially into the device through the SDIO pin on rising edges of the interface clock, SCLK. The data can be transferred MSB first or LSB first, depending on the setting of the LSB-first register bit ...
Page 35
... Rev Page DON'T CARE DON'T CARE DON'T CARE OUTPUT REGISTER DATA t H DON'T CARE DON'T CARE OUTPUT REGISTER DATA t H DON'T CARE DON'T CARE DON'T CARE OUTPUT REGISTER DATA AD9863 ...
Page 36
... AD9863 CLOCK DISTRIBUTION BLOCK Theory/Description The AD9863 uses a PLL clock multiplier circuit and an internal distribution block to generate all required clocks for various timing configurations. The AD9863 has two independent input clocks, CLKIN1 and CLKIN2. The CLKIN1 is primarily used to drive the Rx ADCs path. The CLKIN2 is primarily used to drive the TxDACs path ...
Page 37
... IFACE2 pin can be used to invert the IFACE2 output. Configuration The AD9863 timing for the transmit path and for the receive path depend on the mode setting and various programmable options. The registers that affect the output clock timing and ...
Page 38
... HOLD IFACE3 (CLKOUT) Tx DATA Figure 59. Tx Data Timing Diagram Table 23 shows typical setup and hold times for the AD9863 in the various mode configurations. Function 0: There is no clock output from IFACE2 pin, except in FD mode. 1: The IFACE2 pin outputs a continuous reference clock from the PLL output mode, this inverts the IFACE2 output ...
Page 39
... Configuration Without Serial Port Interface (Using Mode Pins) The AD9863 can be configured using mode pins if a serial port interface is not available. This section applies only to configuring the AD9863 without an SPI. Refer to the Configuring with Mode Pins section of the data sheet for more information. ...
Page 40
... AD9863BCP-50 −40°C to +85°C AD9863BCPRL-50 −40°C to +85°C 1 AD9863BCPZ-50 −40°C to +85°C AD9863BCPZRL-50 1 −40°C to +85°C AD9863-50EB Pb-free part. © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...