AD9863 Analog Devices, AD9863 Datasheet - Page 38

• Manufacturer Part Number: AD9863
• Description: 12-Bit Mixed-Signal Front-End (MxFE® )Processor For Broadband Applications
• Manufacturer: Analog Devices

Specifications of AD9863

• Resolution (bits): 12bit
• # Chan: 2
• Sample Rate: 50MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9863
Table 22. Serial Registers Related to the Clock Distribution Block
Register Name
Enable IFACE2 clkout
Inv clkout (IFACE3)
Tx Inverse Sample
Interpolation Control
PLL_Bypass
ADC Clock Div
Alt Timing Mode
PLL Div5
PLL Multiplier
PLL to IFACE2
Transmit (Tx) timing requires specific setup and hold times to
properly latch data through the data interface bus. These timing
parameters are specified relative to an internally generated
output reference clock. The AD9863 has two interface clocks
provided through the IFACE3 and IFACE2 pins. The transmit
timing specifications and setup and hold times provide a
minimum required window of valid data.
Setup time (t
to a valid logic level prior to the relative output timing edge.
Hold time (t
valid data must remain on the data bus to be properly latched.
Figure 59 shows t
Note that in some cases negative time is specified, for example,
with t
before the relative output clock edge.
Table 23 shows typical setup and hold times for the AD9863 in
the various mode configurations.
HOLD
IFACE3 (CLKOUT)
timing, which means that the hold time edge occurs
HOLD
SETUP
Tx DATA
) is the time after the output timing edge that
) is the time required for data to initially settle
SETUP
Figure 59. Tx Data Timing Diagram
and t
Register Address,
Bit(s)
Register 0x01, Bit 2
Register 0x01, Bit 1
Register 0x13, Bit 5
Register 0x13, Bit 1:0
Register 0x15, Bit 7
Register 0x15, Bit 5
Register 0x15, Bit 4
Register 0x15, Bit 3
Register 0x15, Bit 2:0
Register 0x16, Bit 5
HOLD
relative to IFACE3 falling edge.
t
SETUP
t
HOLD
Function
0: There is no clock output from IFACE2 pin, except in FD mode.
1: The IFACE2 pin outputs a continuous reference clock from the PLL output. In FD mode,
this inverts the IFACE2 output.
0: The IFACE3 clock output is not inverted.
1: The IFACE3 clock output is inverted.
0: The Tx path data is latched relative to the output Tx clock rising edge.
1: The Tx path data is latched relative to the output Tx clock falling edge.
Sets interpolation of 1×, 2×, or 4× for the Tx path.
0: PLL block is used to generate system clock.
1: PLL block bypasses generate system clock.
0: ADC clock rate equals the Rx path frequency.
1: ADC clock is one-half the Rx path frequency.
0: CLKIN1 is used to drive the Rx path clock.
1: PLL block output is used to drive the Rx path clock.
0: PLL block output clock is not divided down.
1: PLL block output clock is divided by 5.
Sets multiplication factor of the PLL block to 1× (000), 2× (001), 4× (010), 8× (011), or 16x (100).
0: If enable IFACE2 clkout register is set, IFACE2 outputs buffered CLKIN.
1: If enable IFACE2 clkout register is set, IFACE2 outputs buffered PLL output clock.
Rev. A| Page 38 of 40
Table 23. Typical Tx Data Latch Timing Relative to
IFACE3 Falling Edge
Mode No.
1
2
4
5
7
8
10
Receive (Rx) path data is output after a reference output clock
edge. The time delay of the Rx data relative to a reference
output clock is called the output delay, t
possible interface clocks provided through the IFACE3 and
IFACE2 pins. Figure 60 shows t
edge. Note that in some cases negative time is specified, which
means that the output data transition occurs prior to the relative
output clock edge.
IFACE3 (CLKOUT)
Rx DATA
Mode Name
FD
Optional FD
HD24
Optional HD24
HD12
Optional HD12
Clone
Figure 60. Rx Data Timing Diagram
t
OD
OD
relative to the IFACE3 rising
t
5
5
5
5
5
5
5
SETUP
OD
(ns)
. The AD9863 has two
t
–2.5
–2.5
–1.5
–1.5
–2.5
–2.5
–1.5
HOLD
(ns)