AD9864 Analog Devices, AD9864 Datasheet
AD9864
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AD9864 Summary of contents
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... MHz to 300 MHz IF input with a signal bandwidth ranging from 6.8 kHz to 270 kHz. The signal chain of the AD9864 consists of a low noise amplifier (LNA), a mixer, a band-pass Σ-Δ analog-to-digital converter (ADC), and a deci- mation filter with programmable decimation factor. An auto- matic gain control (AGC) circuit gives the AD9864 continuous gain adjustment ...
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... AD9864 TABLE OF CONTENTS General Description ......................................................................... 3 AD9864 Specifications..................................................................... 4 Digital Specifications........................................................................ 6 Absolute Maximum Ratings............................................................ 7 Thermal Resistance ...................................................................... 7 Pin Configuration and Functional Descriptions.......................... 8 Definition of Specifications/Test Methods ............................... 9 Typical Performance Characteristics ........................................... 10 Serial Peripheral Interface (SPI) ............................................... 15 Theory of Operation ...................................................................... 17 Serial Port Interface (SPI).......................................................... 17 Synchronous Serial Interface (SSI)........................................... 18 Syncronization Using SYNCB .................................................. 22 Interfacing to DSPs ...
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... MHz to 300 MHz IF input with a signal bandwidth ranging from 6.8 kHz to 270 kHz. The signal chain of the AD9864 consists of an LNA, a mixer, a band-pass Σ-∆ ADC, and a decimation filter with programmable decimation factor. The input LNA is a fixed gain block with an input impedance of approximately 370 Ω ...
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... AD9864 AD9864 SPECIFICATIONS Table 1. VDDI = VDDF = VDDA = VDDC = VDDL = VDDH = 2 3.6 V, VDDQ = VDDP = 2 5 109.65 MHz 107.4 MHz 16.8 MHz, unless otherwise noted. Standard operating mode: VGA at minimum attenuation IF LO REF setting, synthesizers in normal (not fast acquire) mode, decimation factor = 900, 16-bit digital output, and 10 pF load on SSI output pins. ...
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... OPERATING TEMPERATURE RANGE 1 VDDH must be less than VDDD + 0 Clock VCO off and additional 0.7 mA with VGA @ maximum attenuation. Temperature Test Level Min Full VI 2.7 Full VI 2.7 Full VI 1.8 Full VI 2.7 Full VI Full VI –40 Rev Page AD9864 Typ Max Unit 3.0 3.6 V 3.0 3.6 V 3.6 V 5.0 5 0.01 mA +85 °C ...
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... AD9864 DIGITAL SPECIFICATIONS Table 2. VDDI = VDDF = VDDA = VDDC = VDDL = VDDH = 2 3.6 V, VDDQ = VDDP = 2 5 109.65 MHz 107.4 MHz 16.8 MHz, unless otherwise noted. Standard operating mode: VGA at minimum attenuation IF LO REF setting, synthesizers in normal (not fast acquire) mode, decimation factor = 900, 16-bit digital output, and 10 pF load on SSI output pins. ...
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... ABSOLUTE MAXIMUM RATINGS Table 3. AD9864 Absolute Maximum Ratings Parameter VDDF, VDDA, VDDC, VDDD, VDDH, VDDL, VDDI VDDF, VDDA, VDDC, VDDD, VDDH, VDDL, VDDI VDDP, VDDQ GNDF, GNDA, GNDC, GNDD, GNDH, GNDL, GNDI, GNDQ, GNDP, GNDS MXOP, MXON, LOP, LON, IFIN, CXIF, CXVL, CXVM ...
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... Enable Input for SPI Port 26 VDDD Positive Supply for Internal Digital MXOP 1 PIN 1 MXON 2 IDENTIFIER GNDF 3 IF2N 4 IF2P 5 AD9864 VDDF 6 TOP VIEW GCP 7 (Not to Scale) GCN 8 VDDA 9 GNDA 10 VREFP 11 VREFN Pin No ...
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... In the OUT case of the AD9864 often a degradation in noise figure at increased VGA attenuation settings that limits its dynamic range. The test method for the AD9864 is as follows. The small target signal (an unmodulated carrier) is input at the center of the IF ...
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... AD9864 TYPICAL PERFORMANCE CHARACTERISTICS 9.5 9.0 +85°C 8.5 8.0 +25°C 7.5 7.0 –40°C 6.5 6.0 2.7 3.0 VDDx (V) Figure 3. SSB Noise Figure vs. Supply 98 97 +25° +85° 2.7 3.0 VDDx (V) Figure 4. Dynamic Range vs. Supply –29.5 –30.0 –30.5 –31.0 –31.5 –32.0 2.7 3.0 VDDx (V) Figure 5. Minimum VGA Attenuation Clip Point vs. Supply 3.3 3.6 –40°C 3 ...
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... IFIN (dBm) Figure 13. IMD vs. IFIN 16-BIT DATA 16-BIT DATA WITH DVGA ENABLED 24-BIT DATA 100 CHANNEL BANDWIDTH (kHz MSPS) CLK AD9864 –3 –0 –15 –18 –21 –24 –27 –30 –33 –36 –39 –42 –45 –30 1000 ...
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... AD9864 10.0 9.5 16-BIT DATA 9.0 8.5 8.0 7.5 10 100 CHANNEL BANDWIDTH (kHz) Figure 15. Noise Figure vs. BW (Minimum Attenuation 75kHz ( 50kHz ( VGA ATTENUATION (dB) Figure 16. Noise Figure vs. VGA Attenuation (f –30 –40 –50 PIN –60 –70 –80 –90 – ...
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... MSPS) CLK AGC NOISE FIGURE –50 –45 –40 –35 –30 –25 –20 –15 –10 INTERFERER LEVEL (dBm) Figure 26. Noise Figure vs. Interferer Level (16-Bit Data 12.5 kHz, AGCR = 110 kHz) INTERFERER IF AD9864 450 500 450 500 128 112 –5 ...
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... AD9864 16 15 AGC ATTN NOISE FIGURE –50 –45 –40 –35 –30 –25 INTERFERER LEVEL (dBm) Figure 27. Noise Figure vs. Interferer Level (16-Bit Data with DVGA 12.5 kHz, AGCR = 1, f INTERFERER 256 16 224 15 192 14 160 13 128 –20 – ...
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... Reference frequency divisor (6 MSBs of a 14-bit word). 0x38 CKR (7:0) Reference frequency divisor (8 LSBs of a 14-bit word). Default yields 300 kHz from f Maximum = 16383. 0x00 CKN (12:8) Synthesized frequency divisor (5 MSBs of a 13-bit word). Rev Page AD9864 = 16.8 MHz. REF = 16.8 MHz; Minimum = 3, REF ...
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... AD9864 Bit Address (Hex) Breakdown Width 0x13 (7:0) 8 0x14 (6) 1 (5) 1 (4:2) 3 (1:0) 2 0x15 (5:0) 6 0x16 (7:0) 8 SSI CONTROL 0x18 (7:0) 8 0x19 (7:0) 8 0x1A (3:0) 4 ADC TUNING 0x1C (1) 1 (0) 1 0x1D (3:0) 3 0x1E (5:0) 6 0x1F (7:0) 8 TEST REGISTERS AND SPI PORT READ ENABLE 0x37–0x39 (7:0) 8 0x3A (7:4) 4 (3) 1 (2:0) 3 0x3B (7:4) 4 (3) 1 (2:0) 3 0x3C– ...
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... THEORY OF OPERATION SERIAL PORT INTERFACE (SPI) The serial port of the AD9864 has 3-wire or 4-wire SPI capabil- ity, allowing read/write access to all registers that configure the device’s internal parameters. The default 3-wire serial commu- nication port consists of a clock (PC), peripheral enable (PE), and bidirectional data (PD) signal ...
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... SSICRA, SSICRB, and SSIORD. Table 8 shows the different bit fields associated with these registers. The primary output of the AD9864 is the converted I and Q demodulated signal available from the SSI port as a serial bit stream contained within a frame. The output frame rate is equal ...
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... Invert CLKOUT. Enable 4-Wire SPI Interface for SPI Read Operation via DOUTB. I/Q Data-Word Width ( Bit, 1 Bit–24 Bit). Automatically 16-Bit when the AGCV = 1). FS, CLKOUT, and DOUT Drive Strength. Output Bit Rate Divisor /SSIORD. CLKOUT CLK Rev Page AD9864 ...
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... AD9864 CLKOUT FS DOUT SCKI = 0, SCKT = 0, SLFS = 0, SFSI = 0, EFS = 0, SFST = 0, EAGC = 0 CLKOUT FS DOUT SCKI = 0, SCKT = 0, SLFS = 1, SFSI = 0, EFS = 0, SFST = 0, EAGC = 0 CLKOUT FS DOUT SCKI = 0, SCKT = 0, SLFS = 0, SFSI = 0, EFS = 0, SFST = 0, EAGC = 1, AAGC CLKOUT FS DOUT IDLE (HIGH) BITS SCKI = 0, SCKT = 0, SLFS = X, SFSI = X, EFS = 1, SFST = 1, EAGC = 0 SCKI = 0, SCKT = 0, SLFS = X, SFSI = X, EFS = 1, SFST = 0, EAGC = 0 ...
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... CLKOUT or FS modes, with t 0 69* relative to the falling edge of the CLK and/or FS. 1 59* The AD9864 also provides the means for controlling the NA 48 switching characteristics of the digital output signals via the DS NA 69* (drive strength) field of the SSICRB. This feature is useful in ...
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... SYNCRONIZATION USING SYNCB Many applications require the ability to synchronize one or more AD9864s in a way that causes the output data to be pre- cisely aligned to an external asynchronous signal. For example, receiver applications employing diversity often require syn- chronization of multiple AD9864s’ digital outputs. Satellite ...
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... POWER CONTROL To allow power consumption to be minimized, the AD9864 possesses numerous SPI programmable power-down and bias control bits. The AD9864 powers up with all of its functional blocks placed into a standby state, i.e., STBY register default is 0xFF. Each major block may then be powered up by writing the appropriate bit of the STBY register ...
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... Analog Dialogue) can be found on the Analog Devices website. Also, a free software copy of the Analog Devices’ ADIsimPLL, a PLL synthesizer simulation tool, is available at www.analog.com. Note that the ADF4112 model can be used as a close approximation to the AD9864’s LO synthesizer when using this software tool. LOP LO ...
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... I (CKO) setting, while Figure 42 shows that the higher charge pump values provide the optimum performance for the given loop filter configuration. The AD9864 clock synthesizer and oscillator were set up to provide an f external f values were selected for the synthesizer: R VDDC = 3 ...
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... CKTM 0x0 CKFA (13:8) 0x04 CKFA (7:0) Figure 45. The Shunt Capacitance vs. the Frequency of the AD9864’s IF1 Input The mixer’s differential LO port is driven by the LO buffer stage shown in Figure 43, which can be driven single-ended or differential. Since it is self-biasing, the LO signal level can be L ac-coupled and range from 0.3 V p-p to 1.0 V p-p with negligi- ble effect on performance. The mixer’ ...
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... AD9864’s on-chip programmable capacitor array. Since the programming range of the capacitor array is at least 160 pF, the AD9864 has plenty of range to make up for the tol- erances of low cost external components. Note that if f increased by a factor of 1.44 MHz to 26 MHz so that f becomes 3.25 MHz, reducing L and C by approximately the same factor (i.e 6.9 µ ...
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... SPI port. The capacitors of the active RC resonator are similarly programmable. Note that the AD9864 can be placed in and out of its standby mode with- out retuning since the tuning codes are stored in the SPI Registers. When tuning the LC tank, the sampling clock frequency must be stable and the LNA/mixer, LO synthesizer, and ADC must all be placed in standby ...
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... MHz, OSR = 900) OUT CLK 0 –20 ± 135.466kHz PASS BAND –40 –60 –98dB –80 –115dB –100 –120 0 1.0 2.0 0.5 1.5 FREQUENCY (MHz) EQUENCY Figure 53. Decimation Filter Frequency Response for f = 541.666 kSPS ( MHz, OSR = 48) OUT CLK AD9864 –103dB 80 90 100 –94dB 2.5 ...
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... The purpose of the VGA is to extend the usable dynamic range of the AD9864 by allowing the ADC to digitize a desired signal over a large input power range as well as recover a low level signal in the presence of larger unfiltered interferers without saturating or clipping the ADC. ...
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... The MSB of this register is the bit that CLK enables attenuation in the mixer. This feature allows the AD9864 to cope with large level signals beyond the VGA’s range (i.e., > –18 dBm at LNA input) to prevent overloading of the ADC. The lower 15 bits specify the attenuation in the remainder of the signal path. If the DVGA is enabled, the attenuation range is from – ...
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... The number of overload and ADC reset occurrences within the final I/Q update rate of the AD9864, as well as the AGC value (8 MSB), can be read from the SSI data upon proper configuration. The AGC performs digital signal estimation at the output of the first decimation stage (DEC1) as well as the DVGA output that follows the last decimation stage (DEC3) ...
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... The latter difficulty results from the large delay of the decimation filters, DEC2 and DEC3, when one implements a large decimation factor result, given an Rev Page AGCO = 7 AGCO = 4 AGCD = 0 0.1 0.7 0.8 0.9 0.2 0.3 0.6 0.4 0.5 TIME (ms) CLK = 300 kSPS, Decimate by 60 and AGCA = AGCD = π AD9864 1 MSPS, (11) ...
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... AD9864 can accommodate an additional 12 dB peak signal level with only a moderate increase in its noise floor. As Figure 64 shows, the AD9864 can achieve an SNR in excess of 100 dB in narrow-band applications. To realize the full performance of the AD9864 in such applications recom- mended that the I/Q data be represented with 24 bits. If 16-bit Rev ...
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... SNR = 90.1dBFS carefully to prevent known internally generated spurs from mixing down along with the desired signal, thus degrading the SNR per- formance. The major sources of spurs in the AD9864 are the ADC clock and digital circuitry operating at 1 frequency (f which LO (and therefore IF) frequencies are viable. ...
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... Figure 67. Same as Figure 66 Excluding LO Frequencies Known to Produce Large In-Band Spurs bandwidth of the AD9864. As evidence of this property, Figure 68 shows that the in-band noise is quite constant for LO frequencies ranging from 70 MHz to 71 MHz. 100 150 200 LO FREQUENCY (MHz) ...
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... IF FREQUENCY (MHz) Figure 69. Response of AD9864 to a –20 dBm IF Input when f SPURIOUS RESPONSES The spectral purity of the LO (including its phase noise important consideration since LO spurs can mix with unde- sired signals present at the AD9864’s IFIN input to produce an in-band response. To demonstrate the low LO spur level intro- ...
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... Also not shown is the input impedance matching network used to match the AD9864’s IF input to the external IF filter. Lastly, the loop filter components associated with the LO and CLK synthesizers are not shown. ...
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... The conversion gain of the tuner should be set such that the peak IF input signal level into the AD9864 is no greater than –18 dBm to prevent clipping. The AD9864 down- converts the first IF signal to a second IF that is exactly 1/8 of the Σ ...
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... This configuration results in the best possible re 33 ceiver sensitivity under all blocking conditions. The output of the last SAW filters drives the two AD9864s via a direct signal path and an attenuated signal path. The direct path corresponds to the AD9864 having the lowest clip point and provides the highest receiver sensitivity with a system noise figure of 4 ...
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... NF = 3dB Figure 73. Example of Split Path Rx Architecture to Increase Receiver Dynamic Range Capabilities Hung Mixer Mode The AD9864 can operate in hung mixer mode by tying one of the LO’s self-biasing inputs to ground, i.e., GNDI, or the positive supply (VDDI). In this mode, the AD9864 acts as a narrow-band, band-pass Σ-∆ ADC, since its mixer passes the IFIN signal without any frequency translation. The IFIN signal must be centered about the resonant frequency of the Σ ...
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... The power supply distribution block provides filtered, adjust- able voltages to the various supply pins of the AD9864. In the IF input signal path, component pads are available to implement different IF impedance matching networks. The LO and CLK signals can be externally applied or internally derived from a user-supplied VCO module interface daughter board ...
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... Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ORDERING GUIDE AD9864 Products Temperature Package AD9864BCPZ* –40°C to +85°C AD9864BCPZRL* – ...
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... AD9864 NOTES © 2003 Analog Devices, Inc. All rights reserved. Trademarks and regis- tered trademarks are the property of their respective companies. C04319-0-8/03(0) Rev Page ...