AD9864 Analog Devices, AD9864 Datasheet - Page 6

• Manufacturer Part Number: AD9864
• Description: IF Digitizing Subsystem
• Manufacturer: Analog Devices

Specifications of AD9864

• Resolution (bits): 24bit
• # Chan: 1
• Sample Rate: 18MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni,SE-Uni
• Adc Architecture: Sigma-Delta
• Pkg Type: CSP

AD9864
DIGITAL SPECIFICATIONS
Table 2. VDDI = VDDF = VDDA = VDDC = VDDL = VDDH = 2.7 V to 3.6 V, VDDQ = VDDP = 2.7 V to 5.5 V, f
f
setting, synthesizers in normal (not fast acquire) mode, decimation factor = 900, 16-bit digital output, and 10 pF load on SSI output pins.
Parameter
DECIMATOR
SPI-READ OPERATION (See Figure 30)
SPI-WRITE OPERATION
SSI
CMOS LOGIC INPUTS
CMOS LOGIC OUTPUTS
1
2
3
4
IF
Programmable in steps of 48 or 60.
CMOS output mode with C
Absolute maximum and minimum input/output levels are VDDH + 0.3 V and –0.3 V.
I
OL
= 109.65 MHz, f
Decimation Factor
Pass-Band Width
Pass-Band Gain Variation
Alias Attenuation
PC Clock Frequency
PC Clock Period (t
PC Clock High (t
PC Clock Low (t
PC to PD Setup Time (t
PC to PD Hold Time (t
PE to PC Setup Time (t
PC to PE Hold Time (t
PC Clock Frequency
PC Clock Period (t
PC Clock High (t
PC Clock Low (t
PC to PD Setup Time (t
PC to PD Hold Time (t
PC to PD (or DOUTB) Data Valid Time (t
PE to PD Output Valid to Hi-Z (t
CLKOUT Frequency
CLKOUT Period (t
CLKOUT Duty Cycle (t
CLKOUT to FS Valid Time (t
CLKOUT to DOUT Data Valid Time (t
Logic 1 Voltage (V
Logic 0 Voltage (V
Logic 1 Current (I
Logic 0 Current (I
Input Capacitance
Logic 1 Voltage (V
Logic 0 Voltage (V
2
= 1 mA; specification is also dependent on drive strength setting.
(See Figure 32)
LOW
LOW
HI
HI
LO
IH
IL
)
)
CLK
CLK
CLK
IH
IL
OH
OL
)
1
)
)
3
)
= 107.4 MHz, f
)
)
)
)
)
2
)
)
2, 3, 4
LOAD
H
(See Figure 29)
DH
DH
HI
)
S
DS
DS
)
, t
)
)
)
)
= 10 pF and Drive Strength = 7.
LOW
V
)
)
EZ
)
REF
DV
= 16.8 MHz, unless otherwise noted. Standard operating mode: VGA at minimum attenuation
)
DV
)
Rev. 0 | Page 6 of 44
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test Level
IV
V
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
Min
48
88
100
45
45
2
2
5
5
100
45
45
2
2
3
0.867
38.4
33
–1
–1
VDDH – 0.2
8
50
Typ
50%
10
10
3
VDDH – 0.2
CLK
= 18 MSPS,
Max
960
1.2
10
10
26
1153
67
+1
+1
0.5
0.2
Unit
f
dB
dBm
MHz
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
V
V
µA
µA
pF
V
V
CLKOUT