AD9864 Analog Devices, AD9864 Datasheet - Page 38

• Manufacturer Part Number: AD9864
• Description: IF Digitizing Subsystem
• Manufacturer: Analog Devices

Specifications of AD9864

• Resolution (bits): 24bit
• # Chan: 1
• Sample Rate: 18MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni,SE-Uni
• Adc Architecture: Sigma-Delta
• Pkg Type: CSP

AD9864
The LO, CLK, and IFIN signals are coupled to their respective
inputs using 10 nF capacitors. The output of the mixer is cou-
pled to the input of the ADC using 100 pF. An external 100 kΩ
resistor from the RREF pin to GND sets up the AD9864’s
internal bias currents. VREFP and VREFN provide a differen-
tial reference voltage to the AD9864’s Σ-∆ ADC and must be
decoupled by a 0.01 µF differential capacitor along with two
100 pF capacitors to GND. The remaining capacitors are used
to decouple other sensitive internal nodes to GND.
Although power supply decoupling capacitors are not shown, it
is recommended that a 0.1 µF surface-mount capacitor be
placed as close as possible to each power supply pin for maxi-
mum effectiveness. Also not shown is the input impedance
matching network used to match the AD9864’s IF input to the
external IF filter. Lastly, the loop filter components associated
with the LO and CLK synthesizers are not shown.
LC component values for f
For other clock frequencies, the two inductors and the capaci-
tor of the LC tank should be scaled in inverse proportion to the
INPUT
RF
PRESELECT
FILTER
LNA
TUNER
ADF42xx
PLL SYN
CLK
VCO
REFIN
OSCILLATOR
= 18 MHz are given Figure 70.
CRYSTAL
Figure 71. Typical Dual Conversion Superheterodyne Application Using the AD9864
IF CRYSTAL OR
SAW FILTER
FILTER
LOOP
IF2 =
IFIN
SYNTH.
f
–16dB
LO
LNA
CLK
/8
Rev. 0 | Page 38 of 44
VCO
VDDA
FILTER
LOOP
clock. For example, if f
be = 6.9 µH and the capacitor should be about 120 pF. A toler-
ance of 10% is sufficient for these components since tuning of
the LC tank is performed upon system startup.
APPLICATIONS
SuperHeterodyne Receiver Example
The AD9864 is well suited for analog and/or digital narrow-band
radio systems based on a superheterodyne receiver architecture. The
superheterodyne architecture is noted for achieving exceptional
dynamic range and selectivity by using two or more downconversion
stages to provide amplification of the target signal while filtering the
undesired signals. The AD9864 greatly simplifies the design of these
radio systems by integrating the complete IF strip (excluding the LO
VCO) while providing an I/Q digital output (along with other sys-
tem parameters) for the demodulation of both analog and digital
modulated signals. The AD9864’s exceptional dynamic range often
simplifies the IF filtering requirements and eliminates the need for an
external AGC.
SAMPLE CLOCK
SYNTHESIZER
Σ-∆ ADC
DAC AGC
REFERENCE
DECIMATION
VOLTAGE
FILTER
VDDC
CLK
= 26 MHz, the two inductors should
CONTROL LOGIC
FROM DSP
FORMATTING/SSI
AD9864
SPI
CLKOUT
DOUTA
DOUTB
FS
TO
DSP