AD7484 Analog Devices, AD7484 Datasheet - Page 14

• Manufacturer Part Number: AD7484
• Description: 14-Bit, 3 MSPS SAR ADC
• Manufacturer: Analog Devices

Specifications of AD7484

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 3MSPS
• Interface: Par
• Analog Input Type: SE-Uni
• Ain Range: Uni 2.5V
• Adc Architecture: SAR
• Pkg Type: QFP

AD7484
Figure 18 shows the AD7484 conversion sequence when the
part is put into nap mode after each conversion.
Figure 19 and Figure 20 show a typical graphical representation
of power vs. throughput for the AD7484 when in normal mode
and nap mode, respectively.
In standby mode, all internal circuitry is powered down and the
power consumption of the AD7484 is reduced to 10 µW. The
power-up time necessary before a conversion can be initiated is
longer because more of the internal circuitry has been powered
down. In using the internal reference of the AD7484, the ADC
must be brought out of standby mode 500 ms before a conversion is
initiated. Initiating a conversion before the required power-up time
has elapsed results in incorrect conversion data. If an external
CONVST
BUSY
NAP
90
80
70
60
50
40
30
20
10
90
85
80
75
70
65
60
0
0
0
Figure 19. Normal Mode, Power vs. Throughput
250
300ns
Figure 20. Nap Mode, Power vs. Throughput
500
Figure 18. Nap Mode Power Dissipation
600ns
500
1000
THROUGHPUT (kSPS)
THROUGHPUT (kSPS)
750
1000
1500
2µs
1400ns
1250
2000
1500
2500
1750
2000
3000
Rev. C | Page 14 of 20
reference source is used and kept powered up while the AD7484 is
in standby mode, the power-up time required is reduced to 80 µs.
OFFSET/OVERRANGE
The AD7484 provides a ±8% overrange capability as well as a
programmable offset register. The overrange capability is achieved
by the use of a 15th bit (D14) and the CLIP input. If the CLIP input
is at logic high and the contents of the offset register are 0, then the
AD7484 operates as a normal 14-bit ADC. If the input voltage is
greater than the full-scale voltage, the data output from the ADC is
all 1s. Similarly, if the input voltage is lower than the zero-scale
voltage, the data output from the ADC is all 0s. In this case, D14
acts as an overrange indicator. It is set to 1 if the analog input
voltage is outside the nominal 0 V to 2.5 V range.
The default contents of the offset register are 0. If the offset reg-
ister contains any value other than 0, the contents of the register
are added to the SAR result at the end of conversion. This has the
effect of shifting the transfer function of the ADC as shown in
Figure 21 and Figure 22. However, it should be noted that with
the CLIP input set to logic high, the maximum and minimum
codes that the AD7484 can output are 0x3FFF and 0x0000,
respectively. Further details are given in Table 5 and Table 6.
Figure 21 shows the effect of writing a positive value to the
offset register. For example, if the contents of the offset register
contained the value 1024, then the value of the analog input
voltage for which the ADC transitions from reading all 0s to
000…001 (the bottom reference point) is
The analog input voltage for which the ADC reads full-scale
(0x3FFF) in this example is
The effect of writing a negative value to the offset register is
shown in Figure 22. If a value of −512 is written to the offset
register, the bottom end reference point occurs at
Following this, the analog input voltage needed to produce a
full-scale (0x3FFF) result from the ADC is
0.5 LSB − (1024 LSB) = −156.326 mV
2.5 – 1.5 LSB – (1024 LSB) = 2.34352 V
0.5 LSB – (−512 LSB) = 78.20 mW
2.5 V – 1.5 LSB – (−512 LSB) = 2.5779 V
Figure 21. Transfer Characteristic with Positive Offset
111...111
111...110
111...000
011...111
000...010
000...001
000...000
0V
ANALOG INPUT
+V
1LSB = V
REF
–OFFSET
– 1.5LSB
REF
/16384