AD7484 Analog Devices, AD7484 Datasheet - Page 16

• Manufacturer Part Number: AD7484
• Description: 14-Bit, 3 MSPS SAR ADC
• Manufacturer: Analog Devices

Specifications of AD7484

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 3MSPS
• Interface: Par
• Analog Input Type: SE-Uni
• Ain Range: Uni 2.5V
• Adc Architecture: SAR
• Pkg Type: QFP

AD7484
Data must not be read from the AD7484 while a conversion is
taking place. For this reason, if operating the AD7484 at
throughput speeds greater than 2.5 MSPS, it is necessary to tie
both the CS pin and RD pin on the AD7484 low and use a
buffer on the data lines. This situation may also arise in the case
where a read operation cannot be completed in the time after
the end of one conversion and the start of the quiet period
before the next conversion.
The maximum slew rate at the input of the ADC must be
limited to 500 V/µs while BUSY is low to avoid corrupting the
ongoing conversion. In any multiplexed application where the
channel is switched during conversion, this is to happen as soon
as possible after the
Reading Data from the AD7484
Data is read from the part via a 15-bit parallel data bus with the
standard CS and RD signals. The CS and RD signals are internally
gated to enable the conversion result onto the data bus. The data
lines D0 to D14 leave their high impedance state when both CS
and RD are logic low. Therefore, CS can be permanently tied
logic low if required, and the
conversion result.
t
bus activity before the next conversion is initiated.
Writing to the AD7484
The AD7484 features a user accessible offset register. This allows
the bottom of the transfer function to be shifted by ±200 mV. This
feature is explained in more detail in the Offset/Overrange section.
To write to the offset register, a 15-bit word is written to the
AD7484 with the 12 LSBs containing the offset value in twos
complement format. The 3 MSBs must be set to 0. The offset
value must be within the range −1310 to +1310, corresponding
to an offset from −200 mV to +200 mV. The value written to the
offset register is stored and used until power is removed from the
device, or the device is reset. The value stored may be updated at
any time between conversions by another write to the device.
Table 9 shows some examples of offset register values and their
effective offset voltage. Figure 30 shows a timing diagram for
writing to the AD7484.
Table 9. Offset Register Examples
Code
(Decimal)
−1310
−512
+256
+1310
QUIET
. This is the amount of time that must be left after any data
D14 to D12
000
000
000
000
Figure 29
BUSY falling edge.
shows a timing specification called
RD signal used to access the
D11 to D0 (Twos
Complement)
1010 1110 0010
1110 0000 0000
0001 0000 0000
0101 0001 1110
Offset
(mV)
−200
−78.12
+39.06
+200
Rev. C | Page 16 of 20
Driving the CONVST
To achieve the specified performance from the AD7484, the
CONVST pin must be driven from a low jitter source. Because
the falling edge on the
instant, any jitter that may exist on this edge appears as noise
when the analog input signal contains high frequency components.
The relationship between the analog input frequency (f
jitter (t
For example, if the desired SNR due to jitter is 100 dB with a
maximum full-scale analog input frequency of 1.5 MHz, ignor-
ing all other noise sources, the result is an allowable jitter on the
CONVST falling edge of 1.06 ps. For a 14-bit converter (ideal
SNR = 86.04 dB), the allowable jitter is greater than 1.06 ps, but
due consider-ation must be given to the design of the
circuitry to achieve 14-bit performance with large analog input
frequencies.
Typical Connection
Figure 23 shows a typical connection diagram for the AD7484
operating in Parallel Mode 1. Conversion is initiated by a falling
edge on CONVST . When CONVST goes low, the BUSY signal
goes low, and at the end of conversion, the rising edge of BUSY
is used to activate an interrupt service routine. The CS and
lines are then activated to read the 14 data bits (15 bits if using
the overrange feature).
In
logic output levels being either 0 V or DV
V
example, if DV
by a 3 V supply, the logic output levels are either 0 V or 3 V. This
feature allows the AD7484 to interface to 3 V devices while still
enabling the ADC to process signals at a 5 V supply.
4.75V TO 5.25V
DRIVE
DIGITAL
SUPPLY
Figure 23, the V
ADM809
SNR
controls the voltage value of the output logic signals. For
j
), and resulting SNR is given by
JITTER
0.1µF
10µF
DD
INTERFACE
+
PARALLEL
( )
Figure 23. Typical Connection Diagram
dB
is supplied by a 5 V supply and V
DRIVE
=
1nF
10
CONVST pin determines the sampling
Pin
pin is tied to DV
log
RESET
MODE1
MODE2
WRITE
CLIP
NAP
STBY
D0 TO D13
CS
CONVST
RD
BUSY
V
DRIVE
0.1µF
(
2
AD7484
π
DV
×
DD
f
IN
1
REFOUT
REFSEL
AV
REFIN
×
C
DD
BIAS
t
VIN
DD
j
DD
)
0.1µF
. The voltage applied to
2
, which results in
0.47µF
0.47µF
0V TO 2.5V
1nF
DRIVE
+
4.75V TO 5.25V
47µF
IN
ANALOG
REFERENCE
SUPPLY
is supplied
AD780 2.5V
), timing
CONVST
RD