AD7708 Analog Devices, AD7708 Datasheet

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AD7708

Manufacturer Part Number
AD7708
Description
16-Bit 8/10-Channel, Low Voltage, Low Power, Sigma Delta ADC
Manufacturer
Analog Devices
Datasheet

Specifications of AD7708

Resolution (bits)
16bit
# Chan
10
Sample Rate
n/a
Interface
Ser,SPI
Analog Input Type
Diff-Uni,SE-Uni
Ain Range
(2Vref/PGA Gain) p-p
Adc Architecture
Sigma-Delta
Pkg Type
SOIC,SOP

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a
SPI and QSPI are trademarks of Motorola Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
VREF Select is a trademark of Analog Devices, Inc.
AINCOM
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
CHOP
CHOP
DVDD
MUX
DGND
AVDD
NEG BUF
AGND
POS BUF
AD7708/AD7718
FUNCTIONAL BLOCK DIAGRAM
REFIN2(+)/AIN9
PGA
REFIN(+)
REFIN1(+) REFIN2(–)/AIN10
- ADC
GENERAL DESCRIPTION
The AD7708/AD7718 are complete analog front-ends for low
frequency measurement applications. The AD7718 contains a
24-bit Σ-∆ ADC with PGA and can be configured as 4/5 fully-
differential input channels or 8/10 pseudo-differential input
channels. Two pins on the device are configurable as analog
inputs or reference inputs. The AD7708 is a 16-bit version of
the AD7718. Input signal ranges from 20 mV to 2.56 V can be
directly converted using these ADCs. Signals can be converted
directly from a transducer without the need for signal conditioning.
The device operates from a 32 kHz crystal with an on-board PLL
generating the required internal operating frequency. The output
data rate from the part is software programmable. The peak-to-
peak resolution from the part varies with the programmed gain
and output data rate.
The part operates from a single 3 V or 5 V supply. When operating
from 3 V supplies, the power dissipation for the part is 3.84 mW typ.
Both parts are pin-for-pin compatible allowing an upgradable
path from 16 to 24 bits without the need for hardware modifica-
tions. The AD7708/AD7718 are housed in 28-lead SOIC and
TSSOP packages.
REFIN(–)
8-/10-Channel, Low Voltage,
AVDD
I/O PORT
REFIN1(–)
Low Power, - ADCs
INTERFACE
CONTROL
SERIAL
LOGIC
AND
XTAL1 XTAL2
P2
AD7708/AD7718
OSC
AND
PLL
P1
RESET
DOUT
DIN
SCLK
CS
RDY

AD7708 Summary of contents

Page 1

... ADC with PGA and can be configured as 4/5 fully- differential input channels or 8/10 pseudo-differential input channels. Two pins on the device are configurable as analog inputs or reference inputs. The AD7708 is a 16-bit version of the AD7718. Input signal ranges from 2.56 V can be directly converted using these ADCs. Signals can be converted directly from a transducer without the need for signal conditioning ...

Page 2

... AD7708/AD7718 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1 AD7718 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . 3 AD7708 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . 6 TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . 9 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 10 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 12 PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . 13 ADC CIRCUIT INFORMATION . . . . . . . . . . . . . . . . . . . 15 Signal Chain Overview (CHOP Enabled, CHOP = ADC NOISE PERFORMANCE CHOP ENABLED (CHOP = Signal Chain Overview (CHOP Disabled CHOP = ADC NOISE PERFORMANCE CHOP DISABLED (CHOP = 1) ...

Page 3

... AD7708/AD7718 = MIN Test Conditions CHOP = 1 ± Range ± 2.56 V Range ppm Typical Offset Error is in the order of the noise for the programmed gain and update rate following a ...

Page 4

AD7718–SPECIFICATIONS 2 REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz Crystal Input Buffer Enabled. All specifications T Parameter AD7718 (CHOP ENABLED) Output Update Rate 2 No Missing Codes Resolution Output Noise and Update ...

Page 5

... V min/max 4.75/5.25 V min/max 2.7/3.6 V min/max 4.75/5.25 V min 0.55 mA max 0.65 mA max 1.1 mA max µA max 10 µA max 2 µA max 30 µA max 8 µA max min 100 dB typ AD7708/AD7718 Test Conditions ...

Page 6

... AD7708 SPECIFICATIONS REFIN(+) = 2.5 V; REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz Crystal Input Buffers Enabled. All specifications T T unless otherwise noted.) MAX Parameter AD7708 (CHOP DISABLED) Output Update Rate 2 No Missing Codes Resolution Output Noise and Update Rates Integral Nonlinearity ...

Page 7

... Parameter AD7708 (CHOP ENABLED) Output Update Rate 2 No Missing Codes Resolution Output Noise and Update Rates Integral Nonlinearity 3 Offset Error 4 Offset Error Drift vs. Temp 3 Full-Scale Error 4 Gain Drift vs. Temp ANALOG INPUTS Differential Input Full-Scale Voltage Range Matching Absolute AIN Voltage Limits ...

Page 8

... AD7708 AD7718–SPECIFICATIONS 2 REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz Crystal Input Buffer Enabled. All specifications T Parameter LOGIC INPUTS (Continued) 2 SCLK Only (Schmitt-Triggered Input) V T(+) V T(–) V –V T(+) T(–) V T(+) V T(–) V –V T(+) T(–) 2 XTAL1 Only V , Input Low Voltage ...

Page 9

... SCLK Low Pulsewidth CS Rising Edge to SCLK Edge Hold Time ns min (1.6mA WITH DV I SINK 100 A WITH DV TO OUTPUT 1.6V PIN 50pF I SOURCE (200 A WITH DV 100 A WITH DV DD AD7708/AD7718 ...

Page 10

... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7708/AD7718 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150° ...

Page 11

... SCLK DIN MSB RDY SCLK MSB DOUT AD7708/AD7718 t 16 LSB LSB ...

Page 12

... Serial clock input for data transfers to and from the ADC. The SCLK has a Schmitt-trigger input making an opto-isolated interface more robust. The serial clock can be continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to or from the AD7708/AD7718 in smaller batches of data. PIN FUNCTION DESCRIPTIONS . ...

Page 13

... Chip Select Input. This is an active low logic input used to select the AD7708/AD7718. CS can 21 be used to select the AD7708/AD7718 in systems with more than one device on the serial bus frame synchronization signal in communicating with the device. CS can be hardwired low, allowing the AD7708/AD7718 to be operated in 3-wire mode with SCLK, DIN, and DOUT used to interface with the device ...

Page 14

... AD7708/AD7718 –Typical Performance Characteristics 8389600 REFIN1(+)–REFIN1(– INPUT RANGE = 20mV UPDATE RATE = 19.79Hz 8389400 8389200 8389000 8388800 8388600 8388400 8388200 RMS NOISE = 0.58 V rms 8388000 0 100 200 300 400 500 600 READING NUMBER 3.0 2.56V RANGE 2 ...

Page 15

... The AD7708 offers 16-bit resolution while the AD7718 offers 24-bit resolution. The AD7718 is a pin-for-pin compatible version of the AD7708. The AD7718 offers a direct upgradable path from a 16-bit to a 24-bit system without requiring any hardware changes and only minimal software changes. ...

Page 16

... Normal-mode rejection is the major function of the digital filter on the AD7708/AD7718. The normal mode 50 ± rejection with an SF word typically –100 dB. The 60 ± rejection with typically –100 dB. Simultaneous 50 Hz and 60 Hz rejection of better than achieved with ...

Page 17

... For the unipolar ranges the rms noise numbers will be the same as the bipolar range, but the peak-to-peak resolution is now based on half the signal range which effectively means losing one bit of resolution. AD7708/AD7718 ...

Page 18

... Data Update Word Rate (Hz 105 59.36 12.5 13.5 27 50.56 12.5 13.5 69 19. 255 5. Table IV. Typical Output RMS Noise vs. Input Range and Update Rate for AD7708 with Chop Enabled (CHOP = 0); Output RMS Noise Data Update Word Rate (Hz 105.3 1.50 1.50 23 59.36 1.0 1.02 27 50.56 0.95 0.95 69 19.79 0.60 0.65 255 5 ...

Page 19

... There are sinc The 3 dB frequency for all values of SF obeys the following equation: The following plots show frequency response of the AD7708/ AD7718 digital filter for various filter words. The AD7708/ AD7718 are targeted at multiplexed applications. One of the key requirements in these applications is to optimize the SF word to obtain the maximum filter rejection and 60 Hz while minimizing the channel throughput rate ...

Page 20

... AD7708/AD7718 0 –20 –40 –60 –80 –100 –120 –140 –160 –180 –200 FREQUENCY – OUTPUT DATA RATE = 60.2Hz SETTLING TIME = 49.8ms INPUT BANDWIDTH = 15.5Hz 50Hz REJECTION = –43dB, 50Hz 1Hz REJECTION = –40dB 60Hz REJECTION = –147dB, 60Hz 1Hz REJECTION = –101dB 0 – ...

Page 21

... Word Rate (Hz 1365. 315. 62. 59. 50.57 13 255 16.06 14 Table IX. Typical Output RMS Noise vs. Input Range and Update Rate for AD7708 with Chop Disabled (CHOP = 1); Output RMS Noise Data Update Word Rate (Hz 1365.33 30.31 13 315.08 2.47 66 62.06 0.743 69 59.38 0.961 81 50.57 ...

Page 22

... AD7708/AD7718 ON-CHIP REGISTERS The AD7708 and AD7718 are controlled and configured via a number of on-chip registers which are shown in Figure 15. The first of these registers is the communications register which is used to control all operations on these converters. All communications with these parts must start with a write to the communications register to specify the next operation to be performed ...

Page 23

... I/O port. This register determines the amount of averaging performed by the sinc filter and consequently deter- mines the data update rate of the AD7708/AD7718. The filter register determines the update rate for operation with CHOP enabled and CHOP disabled. Provides the most up-to-date conversion result for the selected channel on the AD7718 ...

Page 24

... Read/Write 24 Bits AD7718 Gain Register Read/Write 24 Bits AD7708 Offset Register Read/Write 16 Bits AD7708 Gain Register Read/Write 16 Bits AD7708 ID Register Read 8 Bits AD7718 ID Register Read 8 Bits Test Registers Read/Write 16 Bits Table XI. Registers—Quick Reference Guide (continued) Default Value 800 000 Hex 5XXXX5 Hex ...

Page 25

... Communications Register. In situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with DIN high returns the AD7708/AD7718 to this default state by resetting the part. Table XII outlines the bit designations for the Communications Register. CR0 through CR7 indicate the bit location, CR denoting the bits are in the Communications Register ...

Page 26

... AD7708/AD7718 Status Register (A3, A2, A1 Power-On-Reset = 00Hex) The ADC Status Register is an 8-bit read-only register. To access the ADC Status Register, the user must write to the Communica- tions Register selecting the next operation read and load Bits A3-A0 with 0, 0, 0,0. Table XIV outlines the bit designations for the Status Register ...

Page 27

... The Mode Register is an 8-bit register from which data can be read or to which data can be written. This register configures the operating modes of the AD7708/AD7718. Table XV outlines the bit designations for the Mode Register. MR7 through MR0 indi- cate the bit location, MR denoting the bits are in the Mode Register. MR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit ...

Page 28

... AD7708/AD7718 Operating Characteristics when Addressing the Mode and Control Registers 1. Any change to the MD bits will immediately reset the ADCs. A write to the MD2–MD0 bits with no change is also treated as a reset. 2. Once the MODE has been written with a calibration mode, the RDY bit (STATUS) is immediately reset and the calibration commences. On completion the appropriate calibration registers are written, the bit in STATUS register is updated and the MD2– ...

Page 29

... Table XVIII. Update Rate vs. SF Word CHOP Enabled f (Hz) t (ms) ADC ADC N/A N/A 105.3 9.52 19.79 50.34 5.35 186.77 AD7708/AD7718 ) = and time (t ) are shown in Table XVIII. ADC ADC CHOP Disabled f ...

Page 30

... The conversion result for the selected ADC channel is stored in the ADC data register (DATA). This register is 16 bits wide on the AD7708 and 24 bits wide on the AD7718. This is a read only register. On completion of a read from this register the RDY bit in the status register is cleared. These ADCs can be operated in either unipolar or bipolar mode of operation. ...

Page 31

... Bipolar Mode With an analog input voltage of (–1.024 V With an analog input voltage the output code is 8000Hex for the AD7708 and 800000Hex for the AD7718. With an analog input voltage of (+1.024 V /GAIN), the output code is FFFF Hex for the AD7708 and FFFFFF Hex for the AD7718. Note the REF analog inputs are pseudo bipolar inputs and the analog input voltage must remain within the common-mode input range at all times ...

Page 32

... AD7708/AD7718 Configuring the AD7708/AD7718 All user-accessible registers on the AD7708 and AD7718 are accessed via the serial interface. Communication with any of these registers is initiated by first writing to the Communica- tions Register. Figures 16, 17, and 18 show flow diagrams for initializing the ADC, a sequence for calibrating the ADC chan- nels, and a routine that cycles through and reads all channels ...

Page 33

... The following are the general programming steps required when reading all channels in a multiplexed application. 1. The AD7708/AD7718 is put into continuous conversion mode. In this mode the part continually converts on the specified channel and the RDY line indicates when valid data is available to be read from the data register ...

Page 34

... The Data Register on the AD7718 is 24 bits wide, the ADC data register on the AD7708 is 16 bits wide, and the offset and gain registers are 16-bit registers on the AD7708 and 24-bit registers on the AD7718; however, data transfers to these registers can consist of multiple 8-bit transfers to the serial port of the microcontroller ...

Page 35

... CS input. The 8XC51 is configured in its Mode 0 serial AD7708/ interface mode. Its serial interface contains a single data line. As AD7718 a result, the DOUT and DIN pins of the AD7708/AD7718 should be connected together with a 10 kΩ pull-up resistor. The serial RESET clock on the 8XC51 idles high between data transfers. The ...

Page 36

... ADSP-2103/ADSP-2105 are configured as active low outputs and the ADSP-2103/ADSP-2105 serial clock line, SCLK, is also configured as an output. The CS for the AD7708/AD7718 is active when either the RFS or TFS outputs from the ADSP-2103/ ADSP-2105 are active. The serial clock rate on the ADSP- 2103/ADSP-2105 should be limited to 3 MHz to ensure correct operation with the AD7708/AD7718 ...

Page 37

... AD7708/ AD7718. The normal mode 50 ± rejection with an SF word typically –100 dB. The 60 ± rejection with typically –100 dB. Simultaneous 50 Hz and 60 Hz rejection of better than achieved with and gives a data update rate of 19 ...

Page 38

... AIN1 input AINCOM is 2.5 V and the AD7708/AD7718 is con- figured for an analog input range of ± 1.28 V, the analog input range on the AIN1 input is 1. 3.78 V (i.e., 2.5 V ± ...

Page 39

... The output code for any analog input voltage on the AD7708 can be represented as follows: Code = (AIN × GAIN × 2 )/(1.024 × where AIN is the analog input voltage, GAIN is the PGA gain, i.e the 2.5 V range and 128 on the 20 mV range. When an ADC is configured for bipolar operation, the coding is offset binary with a negative full-scale voltage resulting in a code of 000 ...

Page 40

... AD7708/AD7718 or a ground loop will result. In these situations it is recommended that ground pins of the AD7708/AD7718 be tied to the AGND plane. In any layout it is implicit that the user keep in mind the flow of currents in the system, ensuring that the paths for all currents are as close as possible to the paths the currents took to reach their destinations ...

Page 41

... In addition, the 3-wire digital interface allows this data acquisition front end to be isolated with just three opto- isolators. The entire system can be operated from a single supply, provided that the input signals to the AD7708/ AD7718’s analog inputs are all of positive polarity. 5V ...

Page 42

... DD Combined Ratiometric and Absolute Value Measurement System The AD7708/AD7718 when operated with CHCON = 0 can be configured for operation as four fully-differential analog inputs or eight pseudo-differential analog inputs with two fully-differential reference inputs. Having the ability to use either REFIN1 or REFIN2 with any channel during the conversion process allows the end user to make both absolute and ratiometric measure- ments as shown in Figure 27 ...

Page 43

... Optimizing Throughput while Maximizing 50 Hz and 60 Hz Rejection in a Multiplexed Data Acquisition System The AD7708/AD7718 can be optimized for one of two modes of operation. Operating the AD7708/AD7718 with chopping enabled (CHOP = 0) optimizes the AD7708/AD7718 for analog performance over channel throughput. Output data rates vary from 5 ...

Page 44

... AD7708/AD7718 PIN 1 0.0118 (0.30) 0.0040 (0.10) PIN 1 0.006 (0.15) 0.002 (0.05) SEATING PLANE OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Plastic SOIC (R-28) 0.7125 (18.10) 0.6969 (17.70 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65 0.3937 (10.00) 0.1043 (2.65) 0.0926 (2.35) 0.0500 SEATING 0.0192 (0.49) 0.0125 (0.32) (1.27) PLANE 0.0138 (0.35) 0.0091 (0.23) BSC 28-Lead Plastic TSSOP (RU-28) 0.386 (9.80) 0.378 (9.60) ...

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