AD7708 Analog Devices, AD7708 Datasheet - Page 28

• Manufacturer Part Number: AD7708
• Description: 16-Bit 8/10-Channel, Low Voltage, Low Power, Sigma Delta ADC
• Manufacturer: Analog Devices

Specifications of AD7708

• Resolution (bits): 16bit
• # Chan: 10
• Sample Rate: n/a
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (2Vref/PGA Gain) p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: SOIC,SOP

AD7708/AD7718
Operating Characteristics when Addressing the Mode and Control Registers
1. Any change to the MD bits will immediately reset the ADCs. A write to the MD2–MD0 bits with no change is also treated as a reset.
2. Once the MODE has been written with a calibration mode, the RDY bit (STATUS) is immediately reset and the calibration
3. Calibrations are performed with the maximum allowable SF value with chop enabled. SF register is reset to user configuration
ADC Control Register (ADCCON): (A3, A2, A1, A0 = 0, 0, 1, 0; Power-On-Reset = 07 Hex)
The ADC Control Register is an 8-bit register from which data can be read or to which data can be written. This register is used to
configure the ADC for range, channel selection, and unipolar or bipolar coding. Table XVI outlines the bit designations for the ADC
control register ADCCON7 through ADCCON0 indicate the bit location, ADCCON denoting the bits are in the ADC Control
Register. ADCCON7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of
that bit.
Bit
Location
ADCCON7
ADCCON6
ADCCON5
ADCCON4
CH3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
ADCCON3
commences. On completion the appropriate calibration registers are written, the bit in STATUS register is updated and the
MD2–MD0 bits are reset to 001 to indicate the ADC is back in idle mode.
after calibration with chop enabled. Calibrations are performed with the selected value of SF when chop is disabled.
ADCCON7 ADCCON6
CH3 (0)
CH2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
U/B
Bit
Mnemonic
CH3
CH2
CH1
CH0
CH1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
CH2 (0)
CH0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Table XVI. ADC Control Register (ADCCON) Bit Designations
ADCCON5
Description
ADC Channel Selection Bits. Written by the user to select either pseudo-differential or fully-
differential input pairs used by the ADC as follows:
Positive
Input
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN1
AIN3
AIN5
AIN7
AIN2
AINCOM
REFIN(+)
OPEN
Unipolar/Bipolar Bit.
Set by user to enable unipolar coding i.e., zero differential input will result in 000000hex
output and a full-scale differential input will result in FFFFFF Hex output when operated in
24-bit mode.
Cleared by user to enable bipolar coding, Negative full-scale differential input will result in an
output code of 000000 Hex, zero differential input will result in an output code of 800000 Hex
and a positive full-scale differential input will result in an output code of FFFFFF Hex.
8-Channel Configuration
CH1 (0)
(CHCON = 0)
ADCCON4
Negative
Input
AINCOM
AINCOM
AINCOM
AINCOM
AINCOM
AINCOM
AINCOM
AINCOM
AIN2
AIN4
AIN6
AIN8
AIN2
AINCOM
REFIN(–)
OPEN
CH0 (0)
ADCCON3
Cal Register
Pair
1
2
3
4
1
2
3
4
1
2
3
4
1
1
1
1
U/B (0)
ADCCON2
RN2 (1)
Positive
Input
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN1
AIN3
AIN5
AIN7
AIN9
AINCOM
AIN9
AIN10
10-Channel Configuration
(CHCON = 1)
ADCCON1
RN1 (1)
Negative
Input
AINCOM
AINCOM
AINCOM
AINCOM
AINCOM
AINCOM
AINCOM
AINCOM
AIN2
AIN4
AIN6
AIN8
AIN10
AINCOM
AINCOM
AINCOM
ADCCON0
RN0 (1)
Cal Register
Pair
1
2
3
4
5
1
2
3
1
2
3
4
5
1
4
5