AD9260 Analog Devices, AD9260 Datasheet - Page 34

• Manufacturer Part Number: AD9260
• Description: 16-Bit High Speed Oversampled A/D Converter
• Manufacturer: Analog Devices

Specifications of AD9260

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 2.5MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 4 V p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: QFP

AD9260
A/D with a total rms jitter of 15 ps, the SNR performance of the
A/D will be limited to 86.5 dB.
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the
AD9260. In fact, the CLK input buffer is internally powered
from the AD9260’s analog supply, AVDD. Thus the CLK
logic high and low input voltage levels are +3.5 V and
+1.0 V, respectively.
Supplies for clock drivers should be separated from the A/D
output driver supplies to avoid modulating the clock signal with
digital noise. Low jitter crystal controlled oscillators make the
best clock sources. If the clock is generated from another type of
source (by gating, dividing, or other method), it should be
retimed by the original clock at the last step.
GROUNDING AND DECOUPLING
Analog and Digital Grounding
Proper grounding is essential in any high speed, high resolution
system. Multilayer printed circuit boards (PCBs) are
recommended to provide optimal grounding and power
schemes. The use of ground and power planes offers
distinct advantages:
1.
2.
3.
These characteristics result in both a reduction of
electromagnetic interference (EMI) and an overall
improvement in performance.
It is important to design a layout that prevents noise from
coupling onto the input signal. Digital signals should not be run
in parallel with input signal traces and should be routed away
from the input circuitry. While the AD9260 features separate
analog and digital ground pins, it should be treated as an analog
component. The AVSS, DVSS and DRVSS pins must be joined
together directly under the AD9260. A solid ground plane under
the A/D is acceptable if the power and ground return currents
are managed carefully. Alternatively, the ground plane under
the A/D may contain serrations to steer currents in predictable
directions where cross-coupling between analog and digital
would otherwise be unavoidable. The AD9260/EB ground
layout, shown in Figure 83, depicts the serrated type of
arrangement. The analog and digital grounds are connected by
a jumper below the A/D.
The minimization of the loop area encompassed by a signal
and its return path.
The minimization of the impedance associated with
ground and power paths.
The inherent distributed capacitor formed by the power
plane, PCB insulation, and ground plane.
Rev. C | Page 34 of 44
Analog and Digital Supply Decoupling
The AD9260 features separate analog, digital, and driver supply
and ground pins, helping to minimize digital corruption of
sensitive analog signals.
Figure 73 shows the power supply rejection ratio vs. frequency
for a 200 mV p-p ripple applied to AVDD, DVDD, and
DAVDD.
In general, AVDD, the analog supply, should be decoupled to
AVSS, the analog common, as close to the chip as physically
possible. Figure 74 shows the recommended decoupling for the
analog supplies; 0.1 µF ceramic chip capacitors should provide
adequately low impedance over a wide frequency range. Note
that the AVDD and AVSS pins are co-located on the AD9260 to
simplify the layout of the decoupling capacitors and provide the
shortest possible PCB trace lengths. The AD9260/EB power
plane layout, shown in Figure 84 depicts a typical arrangement
using a multilayer PCB.
The digital activity on the AD9260 chip falls into two general
categories: digital logic and output drivers. The internal digital
logic draws surges of current, mainly during the clock
transitions. The output drivers draw large current impulses
while the output bits are changing. The size and duration of
these currents are a function of the load on the output bits: large
capacitive loads are to be avoided. Note that the digital logic of
90
85
80
75
70
65
60
55
50
45
40
0.1µF
0.1µF
0
Figure 73. AD9260 PSRR vs. Frequency (8x Mode)
DVDD AND DRVDD
Figure 74. Analog Supply Decoupling
10
1
AVDD
28
29
4
3
AVDD
AVDD
AVSS
AVSS
FREQUENCY (kHz)
AD9260
10
AVDD
2
AVSS
44
38
10
3
0.1µF
10
4