AD5755 Analog Devices, AD5755 Datasheet - Page 37

• Manufacturer Part Number: AD5755
• Description: Quad Channel, 16-Bit, Serial Input,
• Manufacturer: Analog Devices

Specifications of AD5755

• Resolution (bits): 16bit
• Dac Update Rate: 91kSPS
• Dac Settling Time: 11µs
• Max Pos Supply (v): +33V
• Single-supply: No
• Dac Type: I or V Out
• Dac Input Format: SPI

Data Sheet
Software Register
The software register has three functions. It allows the user to
perform a software reset to the part. It can be used to set the
user toggle bit, D11, in the status register. It is also used as part
of the watchdog feature when it is enabled. This feature is useful
to ensure that communication has not been lost between the
MCU and the AD5755 and that the datapath lines are working
properly (that is, SDI, SCLK, and SYNC ).
Table 22. Programming the Software Register
MSB
D15
1
Table 23. Software Register Functions
Bit
User Program
Reset Code/SPI Code
Table 24. Programming the DC-to-DC Control Register
MSB
D15
0
1
Table 25. DC-to-DC Control Register Options
Bit
DC-DC Comp
DC-DC Phase
DC-DC Freq
DC-DC MaxV
X = don’t care.
D14
1
D13
1
Description
Selects between an internal and external compensation resistor for the dc-to-dc converter. See the DC-to-DC
Converter Compensation Capacitors and AICC Supply Requirements—Slewing sections in the Device Features
section for more information.
0 = selects the internal 150 kΩ compensation resistor (default).
1 = bypasses the internal compensation resistor for the dc-to-dc converter. In this mode, an external dc-to-dc
compensation resistor must be used; this is placed at the COMP
compensation capacitor to ground. Typically, a ~50 kΩ resistor is recommended.
User programmable dc-to-dc converter phase (between channels).
00 = all dc-to-dc converters clock on same edge (default).
01 = Channel A and Channel B clock on same edge, Channel C and Channel D clock on opposite edge.
10 = Channel A and Channel C clock on same edge, Channel B and Channel D clock on opposite edge.
11 = Channel A, Channel B, Channel C, and Channel D clock 90° out of phase from each other.
DC-to-dc switching frequency; these are divided down from the internal 13 MHz oscillator (see Figure 68 and
Figure 69).
00 = 250 ± 10% kHz.
01 = 410 ± 10% kHz (default).
10 = 650 ± 10% kHz.
Maximum allowed V
00 = 23 V + 1 V/−1.5 V (default).
01 = 24.5 V ± 1 V.
10 = 27 V ± 1 V.
11 = 29.5 V ± 1V.
D14
0
Description
This bit is mapped to Bit D11 of the status register. When this bit is set to 1, Bit D11 of the status register is
set to 1. Likewise, when D12 is set to 0, Bit D11 of the status register is also set to zero. This feature can be
used to ensure that the SPI pins are working correctly by writing a known bit value to this register and
reading back the corresponding bit from the status register.
Option
Reset code
SPI code
D12 to D7
X
1
BOOST_x
Description
Writing 0x555 to D[11:0] performs a reset of the AD5755.
If the watchdog timer feature is enabled, 0x195 must be written to the software register
(D11 to D0) within the programmed timeout period.
voltage supplied by the dc-to-dc converter.
D6
DC-DC Comp
D13
0
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D5 to D4
DC-DC phase
When the watchdog feature is enabled, the user must write
0x195 to the software register within the timeout period. If this
command is not received within the timeout period, the ALERT
pin signals a fault condition. This is only required when the
watchdog timer function is enabled.
DC-to-DC Control Register
The dc-to-dc control register allows the user control over
the dc-to-dc switching frequency and phase, as well as the
maximum allowable dc-to-dc output voltage. The dc-to-dc
control register options are shown in Table 24 and Table 25.
D12
User program
DCDC_x
D3 to D2
DC-DC Freq
pin in series with the 10 nF dc-to-dc
LSB
D11 to D0
Reset code/SPI code
LSB
D1 to D0
DC-DC MaxV
AD5755