AD5755 Analog Devices, AD5755 Datasheet - Page 42

• Manufacturer Part Number: AD5755
• Description: Quad Channel, 16-Bit, Serial Input,
• Manufacturer: Analog Devices

Specifications of AD5755

• Resolution (bits): 16bit
• Dac Update Rate: 91kSPS
• Dac Settling Time: 11µs
• Max Pos Supply (v): +33V
• Single-supply: No
• Dac Type: I or V Out
• Dac Input Format: SPI

AD5755
DIGITAL SLEW RATE CONTROL
The slew rate control feature of the AD5755 allows the user to
control the rate at which the output value changes. This feature
is available on both the current and voltage outputs. With the
slew rate control feature disabled, the output value changes at a
rate limited by the output drive circuitry and the attached load.
To reduce the slew rate, this can be achieved by enabling the
slew rate control feature. With the feature enabled via the SREN
bit of the slew rate control register (see Table 26), the output,
instead of slewing directly between two values, steps digitally
at a rate defined by two parameters accessible via the slew rate
control register, as shown in Table 26. The parameters are
SR_CLOCK and SR_STEP. SR_CLOCK defines the rate at
which the digital slew is updated, for example, if the selected
update rate is 8 kHz, the output updates every 125 μs. In conjunc-
tion with this, SR_STEP defines by how much the output value
changes at each update. Together, both parameters define the
rate of change of the output value. Table 31 and Table 32 outline
the range of values for both the SR_CLOCK and SR_STEP
parameters.
Table 31. Slew Rate Update Clock Options
SR_CLOCK
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
Table 32. Slew Rate Step Size Options
SR_STEP
000
001
010
011
100
101
110
111
These clock frequencies are divided down from the 13 MHz internal
oscillator. See Table 1, Figure 68, and Figure 69.
Update Clock Frequency (Hz)
64 k
32 k
16 k
8 k
4 k
2 k
1 k
500
250
125
64
32
16
8
4
0.5
Step Size (LSBs)
1
2
4
16
32
64
128
256
1
Rev. A | Page 42 of 52
The following equation describes the slew rate as a function of
the step size, the update clock frequency, and the LSB size:
where:
Slew Time is expressed in seconds.
Output Change is expressed in amps for I
When the slew rate control feature is enabled, all output
changes occur at the programmed slew rate (see the DC-to-DC
Converter Settling Time section for additional information).
For example, if the CLEAR pin is asserted, the output slews to
the clear value at the programmed slew rate (assuming that the
clear channel is enabled to be cleared). If a number of channels
are enabled for slew, care must be taken when asserting the clear
pin. If one of the channels is slewing when clear is asserted,
other channels may change directly to their clear values not
under slew rate control. The update clock frequency for any
given value is the same for all output ranges. The step size,
however, varies across output ranges for a given value of step
size because the LSB size is different for each output range.
POWER DISSIPATION CONTROL
The AD5755 contains integrated dynamic power control using
a dc-to-dc boost converter circuit, allowing reductions in power
consumption from standard designs when using the part in
current output mode.
In standard current input module designs, the load resistor
values can range from typically 50 Ω to 750 Ω. Output module
systems must source enough voltage to meet the compliance
voltage requirement across the full range of load resistor values.
For example, in a 4 mA to 20 mA loop when driving 20 mA, a
compliance voltage of >15 V is required. When driving 20 mA
into a 50 Ω load, only 1 V compliance is required.
The AD5755 circuitry senses the output voltage and regulates
this voltage to meet compliance requirements plus a small
headroom voltage. The AD5755 is capable of driving up to
24 mA through a 1 kΩ load.
DC-TO-DC CONVERTERS
The AD5755 contains four independent dc-to-dc converters.
These are used to provide dynamic control of the V
voltage for each channel (see Figure 72). Figure 78 shows the
discreet components needed for the dc-to-dc circuitry, and the
following sections describe component selection and operation
of this circuitry.
Slew
Step
AV
CC
≥10µF
Time
Size
C
IN
×
=
Update
L
10µH
DCDC
Output
Figure 78. DC-to-DC Circuit
SW
Clock
x
D
Change
C
4.7µF
DCDC
DCDC
Frequency
R
FILTER
10Ω
OUT_x
×
LSB
or volts for V
C
0.1µF
Data Sheet
FILTER
Size
V
BOOST_x
BOOST
OUT_x
supply
.