AD5744R Analog Devices, AD5744R Datasheet - Page 23

• Manufacturer Part Number: AD5744R
• Description: Complete Quad, 14-Bit, High Accuracy, Serial Input, Bipolar Voltage Output D/A Converter
• Manufacturer: Analog Devices

Specifications of AD5744R

• Resolution (bits): 14bit
• Dac Update Rate: 1MSPS
• Dac Settling Time: 8µs
• Max Pos Supply (v): +16.5V
• Single-supply: No
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

Data Sheet
SIMULTANEOUS UPDATING VIA LDAC
Depending on the status of both SYNC and LDAC , and after
data has been transferred into the input register of the DACs,
there are two ways to update the data registers and DAC outputs.
Individual DAC Updating
In individual DAC updating mode, LDAC is held low while data
is being clocked into the input shift register. The addressed
DAC output is updated on the rising edge of SYNC .
Simultaneous Updating of All DACs
In simultaneous updating of all DACs mode, LDAC is held high
while data is being clocked into the input shift register. All DAC
outputs are updated by taking LDAC low any time after SYNC
has been taken high. The update then occurs on the falling edge
of LDAC .
See Figure 41 for a simplified block diagram of the DAC load
circuitry.
Table 7. Ideal Output Voltage to Input Code Relationship—Offset Binary Data Coding
MSB
11
10
10
01
00
Table 8. Ideal Output Voltage to Input Code Relationship—Twos Complement Data Coding
MSB
01
00
00
11
10
REFAB, REFCD
Figure 41. Simplified Serial Interface of Input Loading Circuitry
LDAC
SYNC
SCLK
SDIN
1111
0000
0000
1111
0000
1111
0000
0000
1111
0000
for One DAC Channel
INTERFACE
REGISTER
REGISTER
14-BIT
DAC
INPUT
LOGIC
DATA
Digital Input
Digital Input
1111
0000
0000
1111
0000
1111
0000
0000
1111
0000
I/V AMPLIFIER
OUTPUT
SDO
VOUTx
LSB
1111
0001
0000
1111
0000
LSB
1111
0001
0000
1111
0000
Rev. E | Page 23 of 32
TRANSFER FUNCTION
Table 7 and Table 8 show the ideal input code to output voltage
relationship for offset binary data coding and twos complement
data coding, respectively.
The output voltage expression for the AD5744R is given by
where:
D is the decimal equivalent of the code loaded to the DAC.
V
REFCD pins.
ASYNCHRONOUS CLEAR (CLR)
CLR is a negative edge triggered clear that allows the outputs to
be cleared to either 0 V (twos complement coding) or negative full
scale (offset binary coding). It is necessary to maintain CLR low
for a minimum amount of time for the operation to complete
(see
remains at the cleared value until a new value is programmed.
If CLR is at 0 V at power-on, all DAC outputs are updated with
the clear value. A clear can also be initiated through software by
writing the command of 0x04XXXX to the AD5744R.
REFIN
Analog Output
V
+2 V
+2 V
0 V
−2 V
−2 V
Analog Output
V
+2 V
+2 V
0 V
−2 V
−2 V
Figure 2
OUT
OUT
V
is the reference voltage applied at the REFAB and
OUT
REF
REF
REF
REF
REF
REF
REF
REF
= −2 × V
× (8191/8192)
× (1/8192)
× (1/8192)
× (8191/8192)
× (8191/8192)
× (1/8192)
× (1/8192)
× (8191/8192)
). When the
REFIN
+ 4 × V
CLR signal is returned high, the output
REFIN
⎡
⎢
⎣
16
D
,
384
⎤
⎥
⎦
AD5744R