AD5744R Analog Devices, AD5744R Datasheet - Page 7

• Manufacturer Part Number: AD5744R
• Description: Complete Quad, 14-Bit, High Accuracy, Serial Input, Bipolar Voltage Output D/A Converter
• Manufacturer: Analog Devices

Specifications of AD5744R

• Resolution (bits): 14bit
• Dac Update Rate: 1MSPS
• Dac Settling Time: 8µs
• Max Pos Supply (v): +16.5V
• Single-supply: No
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

Data Sheet
TIMING CHARACTERISTICS
AV
DV
Table 3.
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Guaranteed by design and characterization; not production tested.
All input signals are specified with t
See Figure 2, Figure 3, and Figure 4.
Standalone mode only.
Measured with the load circuit of Figure 5.
Daisy-chain mode only.
4
5, 6
DD
CC
= 11.4 V to 16.5 V, AV
= 2.7 V to 5.25 V, R
1, 2, 3
Limit at T
33
13
13
13
13
90
2
5
1.7
480
10
500
10
10
2
25
13
2
170
LOAD
SS
= 10 kΩ, C
= −11.4 V to −16.5 V, AGND = DGND = REFGND = PGND = 0 V; REFAB = REFCD = 5 V external;
R
= t
MIN
F
= 5 ns (10% to 90% of DV
, T
MAX
L
= 200 pF. All specifications T
ns min
ns min
ns max
ns min
ns min
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
μs min
ns min
μs max
ns min
μs max
ns max
μs max
CC
) and timed from a voltage level of 1.2 V.
Rev. E | Page 7 of 32
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
24
Minimum SYNC high time
Data setup time
Data hold time
SYNC rising edge to LDAC falling edge (all DACs updated)
SYNC rising edge to LDAC falling edge (single DAC updated)
LDAC pulse width low
LDAC falling edge to DAC output response time
DAC output settling time
CLR pulse width low
CLR pulse activation time
SCLK rising edge to SDO valid
SYNC rising edge to SCLK falling edge
SYNC rising edge to DAC output response time (LDAC = 0)
LDAC falling edge to SYNC rising edge
th
SCLK falling edge to SYNC rising edge
MIN
to T
MAX
, unless otherwise noted.
AD5744R