AD5306 Analog Devices, AD5306 Datasheet - Page 4

• Manufacturer Part Number: AD5306
• Manufacturer: Analog Devices

Specifications of AD5306

• Resolution (bits): 8bit
• Dac Update Rate: 167kSPS
• Dac Settling Time: 6µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: I2C/Ser 2-wire,Ser

AD5306/AD5316/AD5326
Parameter
LOGIC INPUTS
LOGIC INPUTS (SCL, SDA)
LOGIC OUTPUT (SDA)
POWER REQUIREMENTS
1
2
3
4
5
6
7
8
Temperature range (A, B versions): −40°C to +105°C; typical at +25°C.
See the Terminology section.
DC specifications tested with the outputs unloaded.
Linearity is tested using a reduced code range: AD5306 (Code 8 to 255); AD5316 (Code 28 to 1023); AD5326 (Code 115 to 4095).
This corresponds to x codes. x = deadband voltage/LSB size.
Guaranteed by design and characterization; not production tested.
For the amplifier output to reach its minimum voltage, the offset error must be negative; for the amplifier output to reach its maximum voltage, V
the offset plus gain error must be positive.
Interface inactive; all DACs active. DAC outputs unloaded.
Short-Circuit Current
Power-Up Time
(Excluding SCL, SDA)
Input Current
V
V
Pin Capacitance
V
V
I
V
C
Glitch Rejection
V
Three-State Leakage Current
V
I
I
Three-State Output
IN
DD
DD
IL
IH
IH
IL
HYST
IN
OL
DD
, Input Leakage Current
, Input Low Voltage
, Input Low Voltage
, Input High Voltage
, Input High Voltage
, Input Capacitance
V
V
V
V
Capacitance
, Output Low Voltage
(Normal Mode)
(Power-Down Mode)
DD
DD
DD
DD
, Input Hysteresis
= 4.5 V to 5.5 V
= 2.5 V to 3.6 V
= 4.5 V to 5.5 V
= 2.5 V to 3.6 V
2
8
6
6
6
Min
1.7
0.7 V
−0.3
0.05 V
2.5
DD
DD
Typ
25
16
2.5
5
3
8
8
500
400
0.3
0.09
A Version
1
Max
±1
0.8
0.6
0.5
V
+0.3 V
±1
50
0.4
0.6
±1
5.5
900
750
1
1
DD
+ 0.3
DD
Rev. F | Page 4 of 24
Min
1.7
0.7 V
−0.3
0.05 V
2.5
DD
DD
Typ
25
16
2.5
5
3
8
8
500
400
0.3
0.09
B Version
1
Max
±1
0.8
0.6
0.5
V
+0.3 V
±1
50
0.4
0.6
±1
5.5
900
750
1
1
DD
+ 0.3
DD
Unit
mA
mA
μs
μA
V
V
V
V
pF
V
μA
V
pF
V
V
V
μA
μA
μA
μs
V
ns
μA
pF
μA
Conditions/Comments
V
V
Coming out of power-
down mode; V
Coming out of power-
down mode; V
V
V
V
V
TTL and 1.8 V CMOS
compatible.
SMBus compatible at
V
SMBus compatible at
V
See Figure 20.
Input filtering suppresses
noise spikes of less than
50 ns.
I
I
V
interface inactive.
All DACs in unbuffered
mode.
Buffered mode, extra
current is typically x mA
per DAC, where
x = 5 μA + V
V
interface inactive.
I
readback on SDA.
I
readback on SDA.
SINK
SINK
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
IH
IH
= 3 μA (max) during
= 1.5 μA (max) during
= V
= V
= 5 V.
= 3 V.
= 5 V ± 10%.
= 3 V ± 10%.
= 2.5 V.
= 2.5 V to 5.5 V;
< 3.6 V.
< 3.6 V.
= 3 mA.
= 6 mA.
DD
DD
REF
and V
and V
= V
REF
DD
,
/R
DD
DD
IL
IL
= GND;
DAC.
= GND;
= 5 V.
= 3 V.