AD5306 Analog Devices, AD5306 Datasheet - Page 8

• Manufacturer Part Number: AD5306
• Manufacturer: Analog Devices

Specifications of AD5306

• Resolution (bits): 8bit
• Dac Update Rate: 167kSPS
• Dac Settling Time: 6µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: I2C/Ser 2-wire,Ser

AD5306/AD5316/AD5326
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Mnemonic
LDAC
V
V
V
V
V
V
V
V
PD
V
GND
SDA
SCL
A0
A1
DD
OUT
OUT
OUT
REF
REF
REF
REF
OUT
A
B
C
D
A
B
C
D
Description
Active Low Control Input. Transfers the contents of the input registers to their respective DAC registers.
Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This
allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently low.
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and the supply should be decoupled
with a10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Reference Input Pin for DAC A. This pin can be configured as a buffered or an unbuffered input depending on
the state of the BUF bit in the input word to DAC A. It has an input range from 0.25 V to V
mode and from 1 V to V
Reference Input Pin for DAC B. This pin can be configured as a buffered or an unbuffered input depending on
the state of the BUF bit in the input word to DAC B. It has an input range from 0.25 V to V
mode and from 1 V to V
Reference Input Pin for DAC C. This pin can be configured as a buffered or an unbuffered input depending on
the state of the BUF bit in the input word to DAC C. It has an input range from 0.25 V to V
mode and from 1 V to V
Reference Input Pin for DAC D. This pin can be configured as a buffered or an unbuffered input depending on
the state of the BUF bit in the input word to DAC D. It has an input range from 0.25 V to V
mode and from 1 V to V
Active Low Control Input. Acts as a hardware power-down option. All DACs go into power-down mode when
this pin is tied low. The DAC outputs go into a high impedance state. The current consumption of the part
drops to 300 nA @ 5 V (90 nA @ 3 V).
Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
Serial Data Line. This is used in conjunction with the SCL line to clock data into the 16-bit input shift register.
It is a bidirectional open-drain data line that should be pulled to the supply with an external pull-up resistor.
Serial Clock Line. This is used in conjunction with the SDA line to clock data into the 16-bit input shift register.
Clock rates of up to 400 kbps can be accommodated in the I
Address Input. Sets the LSB of the 7-bit slave address.
Address Input. Sets the second LSB of the 7-bit slave address.
V
V
V
V
V
V
LDAC
OUT
OUT
OUT
DD
DD
DD
DD
REF
REF
REF
V
DD
in buffered mode.
in buffered mode.
in buffered mode.
in buffered mode.
A
B
C
A
B
C
Figure 3. Pin Configuration
1
2
3
4
5
6
7
8
Rev. F | Page 8 of 24
(Not to Scale)
TOP VIEW
AD5306/
AD5316/
AD5326
16
15
14
13
12
11
10
9
A1
A0
SCL
SDA
GND
V
PD
V
OUT
REF
D
D
2
C-compatible interface.
DD
DD
DD
DD
in unbuffered
in unbuffered
in unbuffered
in unbuffered