ADUC814 Analog Devices, ADUC814 Datasheet
ADUC814
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ADUC814 Summary of contents
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... The part operates from a single supply over the extended temperature range −40°C to +125°C. When operating from 3 V supplies, the power dissipation for the part is below 10 mW. The ADuC814 is housed in a 28-lead TSSOP package. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.326.8703 ® ...
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... Serial Safe Mode ..................................................................... 31 Using Flash/EE Data Memory.................................................. 32 ECON—Flash/EE Memory Control SFR ........................... 32 Flash/EE Memory Timing ........................................................ 33 Using the Flash/EE Memory Interface ................................ 33 Programming a Byte .............................................................. 33 User Interface to Other On-Chip ADuC814 Peripherals.......... 34 DACs ............................................................................................ 34 Using the DACs ...................................................................... 35 On-Chip PLL .............................................................................. 37 Time Interval Counter (TIC).................................................... 38 Watchdog Timer......................................................................... 41 Power Supply Monitor ............................................................... 42 ADuC814 Configuration Register (CFG814) ...
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... Mode 3: 9-Bit UART with Variable Baud Rate....................55 UART Serial Port Baud Rate Generation ............................55 Timer 2 Generated Baud Rates .............................................56 Interrupt System..........................................................................57 Interrupt Priority ....................................................................59 Interrupt Vectors.....................................................................59 ADuC814 Hardware Design Considerations ..............................60 Clock Oscillator...........................................................................60 Power Supplies.............................................................................60 Power Consumption...................................................................60 Power-Saving Modes ..............................................................61 Power-On Reset ......................................................................61 Grounding and Board Layout Recommendations .............61 Other Hardware Considerations ...
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... ADuC814 SPECIFICATIONS Table specifications unless otherwise specified MIN MAX Parameter ADC CHANNEL SPECIFICATIONS A GRADE 2,3 DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity 4, 5 CALIBRATED ENDPOINT ERRORS Offset Error Offset Error Match Gain Error Gain Error Match ...
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... V 4.63 V 3.5 3.5 % max min 2000 2000 ms max 0.8 0.4 V max 2.0 2.0 V min Rev Page ADuC814 Test Conditions 2.5 V internal reference 2.5 V external reference DAC Load to AGND kΩ 100 pF Guaranteed montonic V range REF V range REF AV range DD Of full scale on DAC1 DAC V = 2.5 V REF DAC REF DD Full-scale settling time to within ½ ...
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... ADuC814 Parameter 14 SCLOCK and RESET Only (Schmitt-Triggered Inputs T– V – T– INPUT CURRENTS P1.2–P1.7, DLOAD 15 SCLOCK RESET 15 P1.0, P1.1, Port 3 (includes MISO, MOSI/SDATA and SS ) INPUT CAPACITANCE CRYSTAL OSCILLATOR (XTAL1 AND XTAL2) Logic Inputs, XTAL1 Only V , Input Low Voltage INL V , Input High Voltage ...
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... Rev Page ADuC814 Test Conditions OSC_PD = 1 in PLLCON SFR Controlled via WDCON SFR AV / nom / nom DD DD Core CLK = 2.097 MHz (CD bits in PLLCON = 3) Core CLK = 16 ...
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... ADuC814 1 Temperature range –40ºC to +125ºC. 2 ADC linearity is guaranteed when operating in nonpipelined mode, i.e., ADC conversion followed sequentially by a read of the ADC result. ADC linearity is also guaranteed during normal MicroConverter core operation ADC LSB size = i.e., for internal LSB = 610 µV, and for external V ...
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... JA Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) 1 AGND and DGND are shorted internally on the ADuC814. 2 Applies to Pins P1.2 to P1.7 operating in analog or digital input mode. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges ...
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... ADCCON1 Connect 0.1 µF between this pin and AGND. DGND DLOAD XTAL2 2 27 P3.0/RxD XTAL1 3 26 P3.1/TxD SCLOCK 4 25 P3.2/INT0 P3.7/SDATA/MOSI 5 24 P3.3/INT1 P3.6/MISO 6 23 ADuC814 P3.4/T0/CONVST P3.5/T1/SS/EXTCLK 7 22 TOP VIEW P1.0/T2 P1.7/ADC5/DAC1 8 21 (Not to Scale) P1.1/T2EX P1.6/ADC4/DAC0 9 20 RESET P1.5/ADC3 10 19 P1.2/ADC0 P1.4/ADC2 11 18 P1.3/ADC1 C 12 ...
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... In bit designation tables, set implies a Logic 1 state, and cleared implies a Logic 0 state, unless otherwise stated. • Set and cleared also imply that the bit is set or cleared by the ADuC814 hardware, unless otherwise stated. • User software should not write to reserved or unimplemented bits as they may be used in future products. ...
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... ADuC814 TERMINOLOGY ADC SPECIFICATIONS Integral Nonlinearity This is the maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point1/2 LSB below the first code transition and full scale, a point 1/2 LSB above the last code transition ...
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... ADuC814 under various operating conditions. Note that all typical plots in this section were generated using the ADuC814BRU, i.e., the B-grade part. Figure 3 and Figure 4 show typical ADC integral nonlinearity (INL) errors from ADC Code 0 to Code 4095 and 3 V supplies, respectively ...
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... ADuC814 0.30 0.25 0.20 0.15 0.10 0.05 0 –0.50 –0.10 –0. –0. 152kHz S –0.25 0 511 1023 1535 2047 2559 ADC CODES Figure 7. Typical DNL Error, V 0. 152kHz S 0.20 0.15 0.10 0.05 0 –0.50 –0.10 –0.15 –0.20 –0.25 0 511 1023 1535 2047 2559 ADC CODES Figure 8. Typical DNL Error, V ...
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... Figure 13 and Figure 14 show typical FFT plots for the ADuC814. These plots were generated using an external clock input via P3.5 to achieve coherent sampling. The ADC is using its internal reference (2.5 V) sampling a full-scale, 10 kHz sine wave test tone input at a sampling rate of 149.79 kHz. The resultant FFTs ...
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... The part operates from a single supply. When operating from 3 V supplies, the power dissipation for the part is below 10 mW. The ADuC814 is housed in a 28-lead TSSOP package and is specified for operation over an extended temperature range −40°C to +125°C. ...
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... MEMORY ORGANIZATION The ADuC814 does not have Port 0 and Port 2 pins and therefore does not support external program or data memory interfaces. The device executes code from the internal 8-kByte Flash/EE program memory. This internal code space can be programmed via the UART serial port interface while the device is in-circuit ...
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... The SFR space is mapped to the upper 128 bytes of internal data memory space and is accessed by direct addressing only. It provides an interface between the CPU and all on-chip periph- erals. A block diagram showing the programming model of the ADuC814 via the SFR area is shown in Figure 21. A complete SFR map is shown in Figure 22. 8-kBYTE ELECTRICALLY ...
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... Description 7 SMOD Double UART Baud Rate. 6 SERIPD SPI Power-Down Interrupt Enable. 5 INT0PD INT0 Power-Down Interrupt Enable. 4 RSVD Reserved. 3 GF1 General-Purpose Flag Bit. 2 GF0 General-Purpose Flag Bit Power-Down Mode Enable. 0 IDL Idle Mode Enable. --- GF1 GF0 Rev Page ADuC814 PD IDL ...
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... ADuC814 SPECIAL FUNCTION REGISTERS All registers, except the program counter and the four general- purpose register banks, reside in the SFR area. The SFR registers include control, configuration, and data registers that provide an interface between the CPU and all on-chip peripherals. Figure 22 shows a full SFR memory map and SFR contents on RESET ...
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... Timer 2 can be config- ured to generate a repetitive trigger for ADC conversions. The ADuC814 has a high speed ADC to SPI interface data capture logic implemented on-chip. Once configured, this logic transfers the ADC data to the SPI interface without the need for CPU intervention ...
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... ADuC814 SFR INTERFACE TO ADC BLOCK The ADC operation is fully controlled via three SFRs: ADCCON1, ADCCON2, and ADCCON3. These three registers control the mode of operation. ADCCON1 (ADC CONTROL SFR 1) The ADCCON1 register controls conversion and acquisition times, hardware conversion modes, and power-down modes as detailed below ...
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... X Not a vaild selection. No ADC channel selected Not a valid selection. No ADC channel selected Temperature Sensor 0 1 DAC0 1 0 DAC1 1 1 AGND REF Rev Page ADuC814 CS2 CS1 CS0 ...
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... ADuC814 ADCCON3 (ADC CONTROL SFR 3) The ADCCON3 register controls the operation of various calibration modes as well as giving an indication of ADC busy status. SFR Address F5H SFR Power-On Default 00H BUSY GNCLD Table 8. ADCCON3 SFR Bit Designations Bit No. Name Description 7 BUSY ADC Busy Status Bit. ...
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... CAPACITOR Maximum Ratings. They are not necessary if the op amp is DAC powered from the same supply as the ADuC814 because, in that case, the op amp is unable to generate voltages above V below ground amp of some kind is necessary unless the signal source is very low impedance to begin with. DC leakage currents at the ADuC814 analog inputs can cause measurable dc errors with external source impedances as little as 100 Ω ...
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... REF The acquisition time (T the ADC input circuitry uses to sample the input signal. In most cases, an acquisition time of one ADCCLK provides more than adequate time for the ADuC814 to acquire its signal before pin is REF switching the internal track-and-hold amplifier into hold mode. ...
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... The on-chip ADC has been designed to run at a maximum conversion speed of 4.05 µs (247 kHz sampling rate). When converting at this rate, the ADuC814 MCU has 4.05 µs to read the ADC result and store it in memory for further post processing; otherwise the next ADC sample could be lost. The time to complete a conversion and store the ADC results without errors is known as the throughput rate ...
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... ADCDATAH ADCDATAL Figure 30. High Speed Data Capture Logic Timing (Pipelined Mode) As part of internal factory final test routines, the ADuC814 is calibrated to its offset and gain specifications. The offset and gain coefficients obtained from this factory calibration are stored in non-volatile Flash/EE memory. These are downloaded from the Flash/EE memory to offset and gain calibration registers automatically on a power- reset event ...
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... REF voltage. CALIBRATING THE ADC The ADuC814 has two hardware calibration modes, device calibration and system calibration, that can be easily initiated by the user software. The ADCCON3 SFR is used to calibrate the ADC. See Table 8. Device calibration is so called because the relevant signals used for the calibration are available internally to the ADC ...
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... IN-CIRCUIT 700,000 cycles being typical of operation at 25°C. Retention quantifies the ability of the Flash/EE memory to retain its programmed data over time. Again, the ADuC814 has been qualified in accordance with the formal JEDEC Retention Lifetime Specification (A117 specific junction temperature (T = 55° ...
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... These modes can be independently activated, restricting access to the internal code space. These security modes can be enabled as part of the user interface available on all ADuC814 serial or parallel programming tools referenced on the MicroConverter website at www.analog.com/microconverter. Lock Mode ...
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... BYTE 1 BYTE 2 BYTE 3 BYTE 4 Figure 36. Flash/EE Data Memory Configuration As with other ADuC814 user-peripheral circuits, the interface to this memory space is via a group of registers mapped in the SFR space. EADRL is used to hold the 8-bit address of the page to be accessed. A group of four data registers (EDATA1–4) is used to hold 4-byte page data just accessed ...
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... Table 11. Note that a given mode of operation is initiated as soon as the command word is written to the ECON SFR. The core micro- controller operation on the ADuC814 is idled until the requested program/read or erase mode is completed. In practice, this means that even though the Flash/EE memory ...
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... A summary of the SFRs used to control and configure these peripherals is also given. DACS The ADuC814 incorporates two 12-bit, voltage output DACs on-chip. Each DAC has a rail-to-rail voltage output buffer capa- ble of driving 10 kΩ/100 pF. They have two selectable ranges (an external or the internal band gap 2 ...
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... V –100mV DD DAC0 100mV 50mV The endpoint nonlinearities conceptually illustrated in Figure 39 get worse as a function of output loading. Most ADuC814 specifications assume a 10 kΩ resistive load to ground at the DAC output. As the output is forced to source or sink more REF current, the nonlinear regions at the top or bottom (respectively) of Figure 39 become larger ...
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... DAC output. Assuming this resistor is in place, the DAC outputs remain at ground potential whenever the DAC is disabled REF DD Rev Page DAC0 ADuC814 DAC1 Figure 42. Buffering the DAC Outputs ...
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... ON-CHIP PLL The ADuC814 is intended for use with a 32.768 kHz watch crystal. An on-board PLL locks onto a multiple (512) of this 32.768kHz frequency to provide a stable 16.777216 MHz clock for the system. The core can operate at this frequency or at binary submultiples allow power saving in cases where maximum core performance is not required ...
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... IEIP2 SFR description under the Interrupt System section.) If the ADuC814 is in power-down mode, again with TIC interrupt enabled, the TII bit wakes up the device and resumes code execu- tion by vectoring directly to the TIC interrupt service vector address at 0053H ...
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... CARRY bit jump to NOTSET, else continue with next line TIMECON,#01000000B ;If CARRY bit = 1 for last line, then logical OR TIMECON with 40H ;continuation of normal code from here Interval Timebase 1/128 Second Seconds Minutes Hours Rev Page ADuC814 TII TIEN TCEN ...
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... ADuC814 INTVAL User Time Interval Select Register Function User code writes the required time interval to this register. When the 8-bit interval counter is equal to the time interval value loaded in the INTVAL SFR, the TII bit (TIMECON.2) is set and generates an interrupt if enabled. (See the IEIP2 SFR description in the Interrupt System section.) ...
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... WATCHDOG TIMER The purpose of the watchdog timer is to generate a device reset or interrupt within a reasonable amount of time if the ADuC814 enters an erroneous state, possibly due to a programming error, electrical noise, or RFI. The watchdog function can be disabled by clearing the WDE (watchdog enable) bit in the watchdog control (WDCON) SFR ...
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... ADuC814 POWER SUPPLY MONITOR As its name suggests, the power supply monitor, once enabled, monitors the supply ( the ADuC814. It indicates when DD any of the supply pins drop below one of four user-selectable voltage trip points from 2. 4.63 V. For correct operation of the power supply monitor function greater than 2 ...
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... The ADuC814 is intended for use with a 32.768 kHz watch crystal. The on-chip PLL locks onto a multiple of this to provide a stable 16.777216 MHz clock for the device. On the ADuC814, P3.5 alternate functions include T1 input and slave select in SPI master mode. P3.5 also functions as external clock input, EXTCLK, selected via Bit 1 of the CFG814 SFR ...
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... SPI peripheral. This line is active low. Data is received or transmitted in slave mode only when the SS pin is low, allowing the ADuC814 to be used in single master, multislave SPI configurations. If CPHA = 1, then the SS input may be permanently pulled low. With CPHA = 0, ...
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... SPIDAT register. The SCLOCK bit rate is determined by SPR0 and SPR1 in SPICON. It should also be noted that the SS pin is not used in master mode. If the ADuC814 needs to assert the SS pin on an external slave device, a port digital output pin should be used. In master mode, a byte transmission or reception is initiated by a write to SPIDAT ...
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... ADuC814 COMPATIBLE INTERFACE The ADuC814 supports a 2-wire serial interface mode that compatible. The I C compatible interface shares its pins with the on-chip SPI interface, and therefore the user can enable only one interface or the other at any given time (see the SPE bit in SPICON SFR, Table 18) ...
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... SFR bit definitions. Parallel I/O Ports 1 and 3 The ADuC814 has two input/output ports. In addition to per- forming general-purpose I/O, some ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin ...
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... ADuC814 TIMERS/COUNTERS The ADuC814 has three 16-bit timer/counters: Timer 0, Timer 1, and Timer 2. The timer/counter hardware has been included on-chip to relieve the processor core of the overhead inherent in implementing timer/counter functionality in software. Each timer/counter consists of two 8-bit registers, THx and TLx ( and 2). All three can be configured to operate either as timers or event counters ...
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... TH0 and TL0 Timer 0 high byte and low byte. SFR Address 8CH, 8AH, respectively TH1 and TL1 Timer 1 high byte and low byte. SFR Address 8DH, 8BH, respectively 1 TF0 TR0 IE1 Rev Page ADuC814 1 1 IT1 IE0 IT0 ...
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... ADuC814 TIMER/COUNTER 0 AND 1 OPERATING MODES The following paragraphs describe the operating modes for Timer/Counters 0 and 1. Unless otherwise noted, it should be assumed that these modes of operation are the same for both Timer 0 and Timer 1. Mode 0 (13-Bit Timer/Counter) Mode 0 configures an 8-bit timer/counter with a divide-by-32 prescaler ...
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... Timer/Counter 2 also has two pairs of 8-bit data registers associated with it. These are used as both timer data registers and timer capture/reload registers. TH2 and TL2 Timer 2, data high byte and low byte. SFR Address CDH, CCH, respectively RCAP2H and RCAP2L Timer 2, Capture/Reload byte and low byte. SFR Address CBH, CAH, respectively TCLK EXEN2 TR2 Rev Page ADuC814 CNT2 CAP2 ...
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... ADuC814 TIMER/COUNTER 2 OPERATING MODES This section describes the operating modes for Timer/Counter 2. The operating modes are selected by bits in the T2CON SFR as shown in Table 27. Table 25. Mode Selection in T2CON RCLK (or) TCLK CAP2 TR2 16-Bit Autoreload Mode In autoreload mode, there are two options that are selected by bit EXEN2 in T2CON ...
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... Selected Operating Mode Mode 0: Shift Register, fixed baud rate (Core_Clk/2) Mode 1: 8-bit UART, variable baud rate Mode 2: 9-bit UART, fixed baud rate (Core_Clk/64) or (Core_Clk/32) Mode 3: 9-bit UART, variable baud rate Rev Page ADuC814 UART Serial Port Control Register 98H 00H Yes RB8 ...
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... ADuC814 Mode 0: 8-Bit Shift Register Mode Mode 0 is selected by clearing both the SM0 and SM1 bits in the SFR SCON. Serial data enters and exits through RxD. TxD outputs the shift clock. Eight data bits are transmitted or received. Transmission is initiated by any instruction that writes to SBUF ...
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... Table 27. Commonly Used Baud Rates, Timer 1 Ideal Core SMOD Baud CLK Value 9600 16.78 1 2400 16.78 1 1200 16.78 1 1200 2.10 1 Rev Page ADuC814 SMOD /64) × (Core Clock Frequency) SMOD /32) × SMOD /32) × (Core Clock/ TH1-Reload Actual % Value Baud Error –9 (F7H) 9709 1.14 –36 (DCH) 2427 1.14 –73 (B7H) 1197 0 ...
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... ADuC814 Timer 2 Generated Baud Rates Baud rates can also be generated using Timer 2. Using Timer 2 is similar to using Timer 1 in that the timer must overflow 16 times before a bit is transmitted/received. Because Timer 2 has a 16-bit autoreload mode, a wide range of baud rates is possible using Timer 2. ...
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... INTERRUPT SYSTEM The ADuC814 provides a total of twelve interrupt sources with two priority levels. The control and configuration of the interrupt system is carried out through three interrupt-related SFRs. IE Interrupt Enable Register IP Interrupt Priority Register IEIP2 Secondary Interrupt Enable and Priority Register IE Interrupt Enable Register ...
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... ADuC814 IP Interrupt Priority Register SFR Address B8H Power-On Default 00H Bit Addressable Yes --- PADC Table 30. IP SFR Bit Designations Bit No. Name Description 7 --- Reserved. 6 PADC ADC Interrupt Priority. Written to by user to set interrupt priority level (1 = High Low). 5 PT2 Timer 2 Interrupt Priority. Written to by the user to set interrupt priority level (1 = High Low). ...
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... IE SFR. This is done to ensure that the interrupt is always responded watchdog timeout occurs. The watchdog produces an interrupt only if the watchdog timeout is greater than zero. Rev Page ADuC814 Vector Address 0003H 000BH 0013H ...
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... Connect the ground terminal of each of these capacitors directly to the underlying ground DD plane. Finally, note that, at all times, the analog and digital ground pins on the ADuC814 should be referenced to the same system ground reference point. POWER CONSUMPTION The CORE values given represent the current drawn by DV while the rest (ADC and DAC) are pulled by the AV can be disabled in software when not in use ...
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... Figure 57. Internal POR Operation Grounding and Board Layout Recommendations As with all high resolution data converters, special attention must be paid to grounding and PC board layout of ADuC814 based designs in order to achieve optimum performance from the ADCs and DAC. Although the ADuC814 has separate pins ...
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... ADuC814’s digital inputs, add a series resistor to each relevant line to keep rise and fall times longer than the ADuC814 input pins. A value of 100 Ω or 200 Ω is usually sufficient to prevent high speed signals from coupling capacitively into the ADuC814 and affecting the accuracy of ADC conversions ...
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... OPEN) ANALOG INPUT Single-Pin Emulation Mode Also built into the ADuC814 is a dedicated controller for single- pin in-circuit emulation (ICE) using standard production ADuC814 devices. In this mode, emulation access is gained by connection to a single pin, again the DLOAD pin is used for this function ...
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... LOAD 4 ADuC814 internal PLL locks onto a multiple (512 times) the external crystal frequency of 32.768 kHz to provide a stable 16.777216 MHz internal clock for the system. The core can operate at this frequency binary submultiple called Core_Clk, selected via the PLLCON SFR. 5 This number is measured at the default Core_Clk operating frequency of 2 ...
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... DVXH XHDX LSB BIT 1 Figure 62. UART Timing in Shift Register Mode Rev Page Variable Core_Clk Min Typ Max 12 t CORE 10 t –133 CORE 2 t +133 CORE –117 CORE t XLXL SET RI OR SET TI BIT 6 BIT 6 MSB ADuC814 Unit µ ...
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... ADuC814 Table 36. SPI Master Mode Timing (CPHA = 1) Parameter t SCLOCK Low Pulse Width SL t SCLOCK High Pulse Width SH t Data Output Valid after SCLOCK Edge DAV t Data Input Setup Time before SCLOCK Edge DSU t Data Input Hold Time after SCLOCK Edge DHD ...
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... MSB IN MISO t DSU DAV MSB BITS 6–1 BITS 6–1 t DHD Figure 64. SPI Master Mode Timing (CPHA = 0) Rev Page ADuC814 Min Typ Max 630 630 50 150 100 100 LSB LSB IN ...
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... ADuC814 Table 38. SPI Slave Mode Timing (CPHA = 1) Parameter SCLOCK Edge SS t SCLOCK Low Pulse Width SL t SCLOCK High Pulse Width SH t Data Output Valid after SCLOCK Edge DAV t Data Input Setup Time before SCLOCK Edge DSU t Data Input Hold Time after SCLOCK Edge ...
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... DOSU MOSI MSB IN MISO t DSU DAV MSB BITS 6–1 BITS 6–1 t DHD Figure 66. SPI Slave Mode Timing (CPHA = 0) Rev Page ADuC814 Min Typ Max 0 330 330 50 100 100 SFS t t ...
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... ADuC814 OUTLINE DIMENSIONS PIN 1 0.15 0.05 COPLANARITY 9.80 9.70 9. 4.50 4.40 4. 0.65 BSC 1.20 MAX 0.30 0.20 0.19 SEATING 0.09 PLANE 0.10 COMPLIANT TO JEDEC STANDARDS MO-153AE Figure 67. 28-Lead Thin Shrink Small Outline Package (TSSOP) (RU-28) Dimensions shown in mm Rev Page 6.40 BSC 8 ° 0.75 0 ° 0.60 0.45 ...
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... Thin Shrink Small Outline (TSSOP) Thin Shrink Small Outline (TSSOP) Thin Shrink Small Outline (TSSOP) Thin Shrink Small Outline (TSSOP) Thin Shrink Small Outline (TSSOP) Description Development System for the ADuC814 MicroConverter QuickStart PLUS Development System Rev Page ADuC814 Package Option RU-28 ...
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... ADuC814 NOTES Purchase of licensed components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips Patent Rights to use these components © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...