ADUC814 Analog Devices, ADUC814 Datasheet - Page 17

• Manufacturer Part Number: ADUC814
• Description: Precision Analog Microcontroller: 1.3MIPS 8052 MCU + 8kB Flash + 6-Ch 12-Bit ADC + Dual 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC814

• Mcu Core: 8052
• Mcu Speed (mips): 1.3
• Sram (bytes): 256Bytes
• Gpio Pins: 17
• Adc # Channels: 6

MEMORY ORGANIZATION
The ADuC814 does not have Port 0 and Port 2 pins and
therefore does not support external program or data memory
interfaces. The device executes code from the internal 8-kByte
Flash/EE program memory. This internal code space can be
programmed via the UART serial port interface while the device
is in-circuit. The program memory space of the ADuC814 is
shown in Figure 18.
The data memory address space consists of internal memory
only. The internal memory space is divided into four physically
separate and distinct blocks, namely the lower 128 bytes of
RAM, the upper 128 bytes of RAM, the 128 bytes of special
function register (SFR) area, and a 640-byte Flash/EE data
memory. While the upper 128 bytes of RAM and the SFR area
share the same address locations, they are accessed through
different addressing modes.
The lower 128 bytes of data memory can be accessed through
direct or indirect addressing, the upper 128 bytes of RAM can
be accessed through indirect addressing, and the SFR area is
accessed through direct addressing.
Also, as shown in Figure 19, an additional 640 bytes of Flash/EE
data memory are available to the user and can be accessed
indirectly via a group of control registers mapped into the SFR
area. Access to the Flash/EE data memory is discussed in detail
later as part of the Flash/EE Memory section.
Figure 18. Program Memory Map
1FFFH
0000H
PROGRAM MEMORY SPACE
READ-ONLY
PROGRAM
INTERNAL
FLASH/EE
MEMORY
8 kBYTE
Rev. A | Page 17 of 72
The lower 128 bytes of internal data memory are mapped as
shown in Figure 20. The lowest 32 bytes are grouped into four
banks of eight registers addressed as R0 to R7. The next 16 bytes
(128 bits), locations 20H to 2FH above the register banks, form
a block of directly addressable bit locations at bit addresses 00H
through 7FH. The stack can be located anywhere in the internal
memory address space, and the stack depth can be expanded up
to 256 bytes.
RESET initializes the stack pointer to location 07H and incre-
ments it once to start from location 08H, which is also the first
register (R0) of Register Bank 1. If more than one register bank
is being used, the stack pointer should be initialized to an area
of RAM not used for data storage.
BITS IN PSW
SELECTED
BANKS
VIA
Figure 20. Lower 128 Bytes of Internal Data Memory
11
10
01
00
9FH
00H
LOWER
UPPER
128
128
CONTROL REGISTERS
30H
20H
18H
10H
08H
00H
80H
7FH
FFH
00H
Figure 19. Data Memory Map
FLASH/EE DATA
INDIRECTLY
(PAGE 159)
ACCESSED
640 BYTES
DATA MEMORY
AND INDIRECT
MEMORY
(PAGE 0)
ADDRESSING
ADDRESSING
DATA MEMORY SPACE
ACCESSIBLE
ACCESSIBLE
VIA SFR
INTERNAL
INDIRECT
DIRECT
SPACE
ONLY
READ/WRITE
BY
BY
7FH
2FH
1FH
0FH
17H
07H
ADDRESSING
ACCESSIBLE
REGISTERS
BY DIRECT
FUNCTION
SPECIAL
ONLY
BIT-ADDRESSABLE
BIT ADDRESSES
FOUR BANKS OF EIGHT
REGISTERS
R0 R7
GENERAL-PURPOSE
AREA
RESET VALUE OF
STACK POINTER
FFH
80H
ADuC814