ADUC814 Analog Devices, ADUC814 Datasheet - Page 55

• Manufacturer Part Number: ADUC814
• Description: Precision Analog Microcontroller: 1.3MIPS 8052 MCU + 8kB Flash + 6-Ch 12-Bit ADC + Dual 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC814

• Mcu Core: 8052
• Mcu Speed (mips): 1.3
• Sram (bytes): 256Bytes
• Gpio Pins: 17
• Adc # Channels: 6

Mode 2: 9-Bit UART with Fixed Baud Rate
Mode 2 is selected by setting SM0 and clearing SM1. In this
mode, the UART operates in 9-bit mode with a fixed baud rate.
The baud rate is fixed at Core_Clk/64 by default, although by
setting the SMOD bit in PCON, the frequency can be doubled
to Core_Clk/32. Eleven bits are transmitted or received, a start
bit (Bit 0), eight data bits, a programmable ninth bit, and a stop
bit (Bit 1). The ninth bit is most often used as a parity bit,
although it can be used for anything, including a ninth data bit
if required.
To transmit, the eight data bits must be written into SBUF. The
ninth bit must be written into TB8 in SCON. When
transmission is initiated, the eight data bits (from SBUF) are
loaded into the transmit shift register (LSB first). The contents
of TB8 are loaded into the ninth bit position of the transmit
shift register. The transmission starts at the next valid baud rate
clock. The TI flag is set as soon as the stop bit appears on TxD.
Reception for Mode 2 is similar to that of Mode 1. The eight
data bytes are input at RxD (LSB first) and loaded into the
receive shift register. When all eight bits have been clocked in,
the following events occur:
•
•
•
Mode 3: 9-Bit UART with Variable Baud Rate
Mode 3 is selected by setting both SM0 and SM1. In this mode,
the 8051 UART serial port operates in 9-bit mode with a
variable baud rate determined by either Timer 1 or Timer 2.
The operation of the 9-bit UART is the same as for Mode 2 but
the baud rate can be varied as for Mode 1.
In all four modes, transmission is initiated by any instruction
that uses SBUF as a destination register. Reception is initiated in
Mode 0 by the condition RI = 0 and REN = 1. Reception is
initiated in the other modes by the incoming start bit if REN = 1.
UART Serial Port Baud Rate Generation
In these descriptions that follow, Core Clock Frequency refers to
the core clock frequency selected via the CD0–CD2 bits in the
PLLCON SFR.
The eight bits in the receive shift register are latched into
SBUF.
The ninth data bit is latched into RB8 in SCON.
The receiver interrupt flag (RI) is set if, and only if, the
following conditions are met at the time the final shift
pulse is generated:
o
o
If either of these conditions is not met, the received frame
is irretrievably lost, and RI is not set.
RI = 0
Either SM2 = 0 or
SM2 = 1 and the received stop bit = 1
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Mode 0 Baud Rate Generation
The baud rate in Mode 0 is fixed:
Mode 2 Baud Rate Generation
The baud rate in Mode 2 depends on the value of the SMOD bit
in the PCON SFR. If SMOD = 0, the baud rate is 1/64 of the
core clock. If SMOD = 1, the baud rate is 1/32 of the core clock:
Mode 1 and 3 Baud Rate Generation
The baud rates in Modes 1 and 3 are determined by the over-
flow rate in Timer 1 or Timer 2, or both (one for transmit and
the other for receive).
Timer 1 Generated Baud Rates
When Timer 1 is used as the baud rate generator, the baud rates
in Modes 1 and 3 are determined by the Timer 1 overflow rate
and the value of SMOD as follows:
The Timer 1 interrupt should be disabled in this application.
The timer itself can be configured for either timer or counter
operation, and in any of its three running modes. In the most
typical application, it is configured for timer operation, in the
autoreload mode (high nibble of TMOD = 0100 binary). In that
case, the baud rate is given by the formula
A very low baud rate can also be achieved with Timer 1 by leav-
ing the Timer 1 interrupt enabled, and configuring the timer to
run as a 16-bit timer (high nibble of TMOD = 0100 binary), and
using the Timer 1 interrupt to do a 16-bit software reload.
Table 27 shows some commonly used baud rates and how they
might be calculated from a core clock frequency of 2.0971 MHz
and 16.78 MHz. Generally speaking, a 5% error is tolerable
using asynchronous (start/stop) communications.
Table 27. Commonly Used Baud Rates, Timer 1
Ideal
Baud
9600
2400
1200
1200
Mode 2 Baud Rate = (2
Modes 1 and 3 Baud Rate = (2
Mode 0 Baud Rate = (Core Clock Frequency/12)
Core
CLK
16.78
16.78
16.78
2.10
Modes 1 and 3 Baud Rate = (2
SMOD
Value
1
1
1
1
(Timer 1 Overflow Rate)
(12 × [256 − TH1]))
SMOD
/64) × (Core Clock Frequency)
TH1-Reload
Value
–9 (F7H)
–36 (DCH)
–73 (B7H)
–9 (F7H)
SMOD
/32) × (Core Clock/
SMOD
/32) ×
Actual
Baud
9709
2427
1197
1213
ADuC814
%
Error
1.14
1.14
0.25
1.14