ADP1875 Analog Devices, ADP1875 Datasheet
ADP1875
Related parts for ADP1875
ADP1875 Summary of contents
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... ADP1875 Power Saving Mode (PSM) section for more information). Available in three frequency options (300 kHz, 600 kHz, and 1.0 MHz, plus the PSM option), the ADP1874/ADP1875 are well suited for a wide range of applications that require a single-input power supply range from 2. Low voltage biasing is supplied via internal low dropout regulator (LDO) ...
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... Precision Enable Circuitry ........................................................ 19 Undervoltage Lockout ............................................................... 19 On-Board Low Dropout Regulator.......................................... 20 Thermal Shutdown..................................................................... 20 Programming Resistor (RES) Detect Circuit.......................... 20 Valley Current-Limit Setting .................................................... 20 Hiccup Mode During Short Circuit......................................... 22 Synchronous Rectifier................................................................ 22 ADP1875 Power Saving Mode (PSM) ..................................... 22 REVISION HISTORY 2/11—Revision 0: Initial Version Timer Operation ........................................................................ 23 Pseudo-Fixed Frequency ........................................................... 24 ...
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... IN VREG and VREG_IN tied together and should not be loaded externally because they are intended to only bias internal circuitry C = 4.7 μF to PGND, 0.22 μF to GND, V VREG ADP1874ARQZ-0.3/ADP1875ARQZ-0.3 (300 kHz) ADP1874ARQZ-0.6/ADP1875ARQZ-0.6 (600 kHz) ADP1874ARQZ-1.0/ADP1875ARQZ-1.0 (1.0 MHz 100 100 100 mA, V ...
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... ADP1874/ADP1875 Parameter Symbol ADP1874ARQZ-0.6/ ADP1875ARQZ-0.6 (600 kHz) On-Time Minimum On-Time Minimum Off-Time ADP1874ARQZ-1.0/ ADP1875ARQZ-1.0 (1.0 MHz) On-Time Minimum On-Time Minimum Off-Time OUTPUT DRIVER CHARACTERISTICS High-Side Driver 2 Output Source Resistance 2 Output Sink Resistance 3 Rise Time t r, DRVH 3 Fall Time t f, DRVH Low-Side Driver ...
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... MOSFETs being Infineon BSC042N03MS G. 2 Guaranteed by design. 3 Not automatic test equipment (ATE) tested. Test Conditions/Comments 0.5 V < TRACK < 0.6 V, offset = V − TRACK TRACK 59 and Figure 60), C Rev Page ADP1874/ADP1875 Min Typ Max Unit 4.3 nF, and the upper- and lower-side GATE ...
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... ADP1874/ADP1875 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VREG, VREG_IN, TRACK to PGND, GND VIN, EN, PGOOD to PGND FB, COMP, RES GND DRVL to PGND SW to PGND BST to SW BST to PGND DRVH to SW PGND to GND PGOOD Input Current θ (16-Lead QSOP) JA 4-Layer Board Operating Junction Temperature Range ...
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... Current Sense Gain Resistor (External). Connect a resistor between the RES pin and GND (Pin 5). 7 VREG Internal Regulator Supply Bias Voltage for the ADP1874/ADP1875 Controller (Includes the Output Gate Drivers). A bypass capacitor of 1 μF directly from this pin to PGND and a 0.1 μF across VREG and GND are recommended. 8 VREG_IN Input to the Internal LDO ...
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... ADP1874/ADP1875 TYPICAL PERFORMANCE CHARACTERISTICS 100 13V (PSM 13V 25° 16.5V (PSM 0.8V OUT 300kHz SW 20 WÜRTH INDUCTOR: 15 744325072 0.72µH, DCR = 1.3mΩ 10 INFINEON FETs: 5 BSC042N03MS G (UPPER/LOWER 100 1k LOAD CURRENT (mA) Figure 4. Efficiency—300 kHz, V ...
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... Figure 15. Output Voltage Accuracy—300 kHz, V Rev Page ADP1874/ADP1875 V = 16.5V IN +125°C +25°C –40°C 4000 6000 8000 10,000 LOAD CURRENT (mA) = 0.8 V OUT V = 13V ...
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... ADP1874/ADP1875 0.808 0.806 0.804 0.802 0.800 0.798 0.796 0.794 +125° 13V IN +25° 16.5V –40°C IN 0.792 0 1000 2000 3000 4000 5000 6000 7000 8000 LOAD CURRENT (mA) Figure 16. Output Voltage Accuracy—600 kHz, V 1.818 1.816 1.814 1.812 1.810 1.808 1.806 1.804 1 ...
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... Figure 25. Switching Frequency vs. High Input Voltage, 1.0 MHz, NO LOAD 330 NO LOAD 320 310 300 290 280 270 260 250 240 15.4 15.8 16.2 16.5 = 1.8 V, OUT Rev Page ADP1874/ADP1875 +125°C +25°C –40°C 13.0 13.5 14.0 14.5 15.0 15 Range = 16 280 V = 13V +125°C IN +25°C ...
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... ADP1874/ADP1875 338 V = 13V +125°C IN +25° 16.5V 334 IN –40°C 330 326 322 318 314 310 306 302 298 0 800 1600 2400 3200 4000 4800 5600 LOAD CURRENT (mA) Figure 28. Frequency vs. Load Current, 300 kHz, V +125°C 540 V = 13V IN +25° 16.5V IN – ...
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... Figure 38. Minimum Off-Time vs. Temperature 680 +125°C +25°C 630 –40°C 580 530 480 430 380 330 280 230 180 900 1000 2.7 Figure 39. Minimum Off-Time vs. VREG (Low Input Voltage) Rev Page ADP1874/ADP1875 +125°C +25°C –40°C 7.9 9.1 10.3 11.5 12.7 13.9 15.1 V (V) IN VREG = 2.7V VREG = 3.6V VREG = 5.5V – ...
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... ADP1874/ADP1875 800 VREG = 2.7V +125°C +25°C VREG = 3.6V 720 –40°C VREG = 5.5V 640 560 480 400 320 240 160 80 300 400 500 600 700 FREQUENCY (kHz) Figure 40. Internal Rectifier Drop vs. Frequency 1280 V = 5.5V 1MHz IN 1200 300kHz V = 13V IN 1120 V = 16.5V IN 1040 960 880 800 ...
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... Figure 50. Load Transient Step—Forced PWM at Light Load CH1 3.40A CH1 10A Ω CH3 20V Figure 51. Positive Step During Heavy Load Transient Behavior—Forced PWM at Light Load Rev Page ADP1874/ADP1875 OUTPUT VOLTAGE 12A NEGATIVE STEP SW NODE LOW SIDE B CH2 200mV M20µs A CH1 W CH4 ...
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... ADP1874/ADP1875 OUTPUT VOLTAGE 2 12A NEGATIVE STEP 1 SW NODE 3 LOW SIDE 4 B CH1 10A Ω CH2 200mV M10µs W CH3 20V CH4 5V T 23.8% Figure 52. Negative Step During Heavy Load Transient Behavior—Forced PWM at Light Load (See Figure 99 Application Circuit) OUTPUT VOLTAGE ...
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... A CH2 4.20V = 5 V (Q3)) GS 1.30 LOW SIDE 1.25 1.20 1.15 1.10 ) 1.05 1.00 0.95 0.90 SW NODE 0.85 0.80 0.75 0.70 A CH2 4.20V = 5 V (Q3)) GS Rev Page ADP1874/ADP1875 570 550 530 510 490 470 450 430 –40 – TEMPERATURE (°C) Figure 61. Transconductance (G ) vs. Temperature m 680 630 580 530 480 430 380 330 2 ...
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... TON BG_REF SS COMP PSM IN_PSM HS_O IN_SS IN_HICC PWM IREV PWM IREV COMP CS AMP ADC CS GAIN SET GND RES Figure 64. ADP1874/ADP1875 Block Diagram Rev Page 690mV FB 600mV 530mV VREG (TRIMMED 2RC OUT IN SW FILTER 300kΩ LEVEL ...
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... COMP pin to begin to rise (see Figure 66). Tying the VREG pin to the EN pin via a pull-up resistor causes the voltage at this pin to rise above the enable threshold of 630 mV to enable the ADP1874/ADP1875. SOFT START The ADP1874 employs externally programmable, soft start circuitry that charges up a capacitor tied to the SS pin to GND ...
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... Open 100 kΩ VALLEY CURRENT-LIMIT SETTING The architecture of the ADP1874/ADP1875 is based on valley current-mode control. The current limit is determined by three components: the R sense amplifier output voltage swing, and the current-sense gain. The CS output voltage range is internally fixed at 1.4 V. The ...
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... Because the ADP1874/ADP1875 are based on valley current control, the relationship between I and I CLIM ⎛ − ⎞ × ⎜ I ⎟ CLIM LOAD ⎝ ⎠ 2 where the ratio between the inductor ripple current and the I desired average load current (see Figure 70). ...
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... TO COOL DOWN Figure 73. Idle Mode Entry Sequence Due to Current-Limit Violation ADP1875 POWER SAVING MODE (PSM) A power saving mode is provided in the ADP1875. The ADP1875 operates in the discontinuous conduction mode (DCM) and pulse skips at light load to medium load currents. The controller outputs pulses as necessary to maintain output regulation. Unlike ...
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... Figure 76 Offset to Ensure Prevention of Negative Inductor Current The system remains in idle mode until the output voltage drops below regulation. A PWM pulse is then produced, turning on the upper-side MOSFET to maintain system regulation. The ADP1875 does not have an internal clock switches purely as a hysteretic controller as described in this section. ...
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... V In this case, the switching frequency decreases, or experiences a foldback, to help facilitate output voltage recovery. Because the ADP1874/ADP1875 have the ability to respond rapidly to sudden changes in load demand, the recovery period in which the output voltage settles back to its original steady state operating point is much quicker than it would be for a fixed-frequency equivalent ...
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... OUT2 (SLAVE) 1.2V V OUT2 (SLAVE) VOLTAGE TRACKING The ADP1874/ADP1875 feature a voltage-tracking function that facilitates proper power-up sequencing in applications that require tracking a master voltage. In this manner, the user is free to impose a master voltage that typically comes with a selectable or programmable ramp rate on slave or secondary power rails. ...
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... ADP1874/ADP1875 The slave output tracks the master output dv/dt until the slave output regulation point is reached. Any influence by the master voltage thereafter will no longer be in effect. Ensure that the voltage forced on the slave TRACK pin is above 0 the end of TRACK phase. Voltages imposed on the TRACK pin below 0.7 V, once ...
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... ESR is the equivalent series resistance of the output capacitors. To calculate the output load step, use the following equation where ΔV a given positive load current step (ΔI Rev Page ADP1874/ADP1875 DCR I Dimensions SAT (mΩ) (A) (mm) Manufacturer 0.33 55 10.2 × 7 Würth Elek. ...
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... MLCCs should be mounted in parallel with the electrolytic capacitors to reduce the overall series resistance. COMPENSATION NETWORK Due to its current-mode architecture, the ADP1874/ADP1875 require Type II compensation. To determine the component values needed for compensation (resistance and capacitance values necessary to examine the converter’s overall loop ...
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... C TOTAL R GATE The ratio of this time constant to the period of one switching cycle is the multiplying factor to be used in the following expression Rev Page ADP1874/ADP1875 parameter of the external MOSFETs. GATE [ ( = × ...
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... Ferrite inductors have the lowest core losses, whereas powdered iron inductors have higher core losses recommended to use shielded ferrite core material type inductors with the ADP1874/ADP1875 for a high current, dc-to-dc switching application to achieve minimal loss and negligible electromagnetic interference (EMI). ...
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... MOSFET) IN The maximum junction temperature allowed for the ADP1874/ ADP1875 ICs is 125°C. This means that the sum of the ambient temperature (T caused by the thermal impedance of the package and the internal power dissipation, should not exceed 125°C, as dictated by the ...
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... which is below the maximum junction temperature of 125°C. DESIGN EXAMPLE The ADP1874/ADP1875 are easy to use, requiring only a few design criteria. For example, the example outlined in this section uses only four design criteria 1 OUT (typical), and f = 300 kHz ...
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... REF × 0035 ) . 0 0011 × ) × × 0035 . 0 0011 Rev Page ADP1874/ADP1875 π COMP COMP ZERO 1 = × × × × × 423 pF = 5.4 mΩ (body conduction time (total MOSFET gate charge) = 1.5 Ω ...
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... ADP1874/ADP1875 EXTERNAL COMPONENT RECOMMENDATIONS The configurations listed in Table 10 are with f VREG = 5 V (float), and a maximum load current The ADP1875 models listed in Table 10 are the PSM versions of the device. Table 10. External Component Values Marking Code (First Line/Second Line) SAP Model ADP1874 ADP1874ARQZ-0 ...
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... V (V) C (nF) Q (nC TOTAL Rev Page ADP1874/ADP1875 (μF) (μH) (kΩ) (pF) OUT × 270 0.22 54.9 200 × 330 0.22 49.3 220 × 180 0.22 56.9 130 2 270 4 0.22 54.9 ...
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... COMPENSATION AND FEEDBACK RESISTORS Figure 91. Overall Layout of the ADP1870 High Current Evaluation Board Figure 90 shows the schematic of a typical ADP1874/ADP1875 used for a high current application. Blue traces denote high current pathways. VIN, PGND, and V possibly replicated, descending down into the multiple layers. ...
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... Figure 92. Layer 2 of Evaluation Board TOP RESISTOR FEEDBACK TAP VOUT SENSE TAP LINE EXTENDING BACK TO THE TOP RESISTOR IN THE FEEDBACK DIVIDER NETWORK. THIS OVERLAPS WITH PGND SENSE TAP LINE EXTENDING TO THE ANALOG GROUND PLANE Figure 93. Layer 3 of Evaluation Board Rev Page ADP1874/ADP1875 ...
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... ADP1874/ADP1875 BOTTOM RESISTOR TAP TO ANALOG GROUND PLANE PGND SENSE TAP FROM NEGATIVE TERMINALS OF THE OUTPUT BULK CAPACITORS. THIS TRACK PLACEMENT SHOULD BE DIRECTLY BELOW THE VOUT SENSE LINE OF LAYER 3. IC SECTION (LEFT SIDE OF EVALUATION BOARD) A dedicated plane for the analog ground plane (GND) should be separate from the main power ground plane (PGND) ...
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... DIFFERENTIAL SENSING Because the ADP1874/ADP1875 operate in valley current- mode control, a differential voltage reading is taken across the drain and source of the lower-side MOSFET. The drain of the lower-side MOSFET should be connected as close as possible to the SW pin (Pin 15) of the IC. Likewise, the source should be connected as close as possible to the PGND pin (Pin 13) of the IC ...
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... PANASONIC: (OUTPUT CAPACITORS) 9 REG 270µF, SP-SERIES, 4V, 7mΩ EEFUE0G271LR INFINEON MOSFETs: BSC042N03MS G (LOWER SIDE) BSC080N03MS G (UPPER SIDE) WÜRTH INDUCTORS: 1.2µH, 2.00mΩ, 20A 744325120 HIGH VOLTAGE INPUT ADP1874/ 22µF C ADP1875 BST 100nF BST 1.2µH DRVH 14 R SNB 2Ω ...
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... TRACK PANASONIC: (OUTPUT CAPACITORS REG 270µF, SP-SERIES, 4V, 7mΩ EEFUE0G271LR INFINEON MOSFETs: BSC042N03MS G (LOWER SIDE) BSC080N03MS G (UPPER SIDE) WÜRTH INDUCTORS: 1.2µH, 2.00mΩ, 20A 744325120 Rev Page ADP1874/ADP1875 22µF 22µF 22µF N/A N 1.8V, 12A ...
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... ADP1874-0.3-EVALZ ADP1874-0.6-EVALZ ADP1874-1.0-EVALZ ADP1875ARQZ-0.3-R7 −40°C to +125°C ADP1875ARQZ-0.6-R7 −40°C to +125°C ADP1875ARQZ-1.0-R7 −40°C to +125°C ADP1875-0.3-EVALZ ADP1875-0.6-EVALZ ADP1875-1.0-EVALZ RoHS Compliant Part. 0.197 (5.00) 0.193 (4.90) 0.189 (4.80 0.158 (4.01) 0.154 (3.91) ...
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... NOTES Rev Page ADP1874/ADP1875 ...
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... ADP1874/ADP1875 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09347-0-2/11(0) Rev Page ...