ADP1875 Analog Devices, ADP1875 Datasheet - Page 31

• Manufacturer Part Number: ADP1875
• Description: Synchronous Buck Controller with Constant On-Time, Valley Current Mode, and Power Saving Mode
• Manufacturer: Analog Devices

THERMAL CONSIDERATIONS
The ADP1874/ADP1875 are used for dc-to-dc, step down, high
current applications that have an on-board controller, an on-board
LDO, and on-board MOSFET drivers. Because applications may
require up to 20 A of load current and be subjected to high ambient
temperature, the selection of external upper- and lower-side
MOSFETs must be associated with careful thermal consideration
to not exceed the maximum allowable junction temperature of
125°C. To avoid permanent or irreparable damage, if the junction
temperature reaches or exceeds 155°C, the part enters thermal
shutdown, turning off both external MOSFETs and is not re-
enabled until the junction temperature cools to 140°C (see the
On-Board Low Dropout Regulator section).
In addition, it is important to consider the thermal impedance
of the package. Because the ADP1874/ADP1875 employ an
on-board LDO, the ac current (fxCxV) consumed by the internal
drivers to drive the external MOSFETs, adds another element of
power dissipation across the internal LDO. Equation 3 shows the
power dissipation calculations for the integrated drivers and for
the internal LDO.
Table 9 lists the thermal impedance for the ADP1874/ADP1875,
which are available in a 16-lead QSOP.
Table 9. Thermal Impedance for 16-lead QSOP
Parameter
16-Lead QSOP θ
Figure 89 specifies the maximum allowable ambient temperature
that can surround the ADP1874/ADP1875 IC for a specified
high input voltage (V
derating conditions for each available switching frequency for
low, typical, and high output setpoints for the 16-lead QSOP
package. All temperature derating criteria are based on a
maximum IC junction temperature of 125°C.
4-Layer Board
150
140
130
120
110
100
90
80
70
60
50
40
30
4-Layer EVB, C
5.5
7.0
Figure 89. Ambient Temperature vs. V
JA
600kHz
300kHz
1MHz
8.5
IN
IN
). Figure 89 illustrates the temperature
= 4.3 nF (Upper-/Lower-Side MOSFET)
10.0
11.5
V
V
V
OUT
OUT
OUT
V
IN
Thermal Impedance
104°C/W
13.0
= 0.8V
= 1.8V
= HIGH SETPOINT
(V)
14.5
16.0
IN
,
17.5
19.0
Rev. 0 | Page 31 of 44
The maximum junction temperature allowed for the ADP1874/
ADP1875 ICs is 125°C. This means that the sum of the ambient
temperature (T
caused by the thermal impedance of the package and the internal
power dissipation, should not exceed 125°C, as dictated by the
following expression:
where:
T
T
dissipated from within.
T
The rise in package temperature is directly proportional to its
thermal impedance characteristics. The following equation
represents this proportionality relationship:
where:
θ
the outside surface of the die, where it meets the surrounding air.
P
The bulk of the power dissipated is due to the gate capacitance of
the external MOSFETs and current running through the on-board
LDO. The power loss equations for the MOSFET drivers and
internal low dropout regulator (see the MOSFET Driver Loss
section and the Efficiency Consideration section) are
where:
C
C
I
side drivers.
V
the rectifier drop (see Figure 87)).
VREG is the LDO output/bias voltage.
where:
P
LDO block across VIN and VREG.
P
V
VREG is the LDO output voltage and bias voltage.
C
I
BIAS
BIAS
JA
DR(LOSS)
DISS(LDO)
DR(LOSS)
J
R
A
upperFET
lowerFET
TOTAL
DR
IN
is the maximum junction temperature.
is the rise in package temperature due to the power
is the ambient temperature.
is the thermal resistance of the package from the junction to
is the high voltage input.
is the driver bias voltage (the low input voltage (VREG) minus
is the dc current (2 mA) flowing into the upper- and lower-
is the dc input bias current.
T
T
P
[VREG × (f
P
P
J
R
DR(LOSS)
DISS
DR
is the C
= T
= θ
is the input gate capacitance of the lower-side MOSFET.
is the overall power dissipated by the IC.
is the input gate capacitance of the upper-side MOSFET.
is the MOSFET driver loss.
(
is the power dissipated through the pass device in the
LOSS
(
LDO
R
JA
× T
= [V
× P
)
)
+
GD
A
=
) and the rise in package temperature (T
A
(
SW
DR(LOSS)
V
+ C
DR
C
IN
lowerFET
× (f
GS
−
VREG
of the external MOSFET.
SW
C
VREG + I
upperFET
)
×
(
V
f
SW
ADP1874/ADP1875
DR
BIAS
+ I
×
C
)]
BIAS
TOTAL
)] +
×
VREG
R
+
), which is
I
BIAS
)
(3)
(1)
(2)
(4)