ST7LITE25F2 STMicroelectronics, ST7LITE25F2 Datasheet - Page 113

• Manufacturer Part Number: ST7LITE25F2
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7LITE25F2

• 8 Kbytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55˚C.
• Clock Sources: Internal 1% RC oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt

13.10 COMMUNICATION INTERFACE CHARACTERISTICS
13.10.1 SPI - Serial Peripheral Interface
Subject to general operating conditions for V
f
Figure 86. SPI Slave Timing Diagram with CPHA=0
Notes:
1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xV
4. Depends on f
OSC
1/t
Symbol
t
t
t
t
su(SS)
w(SCKH)
t
w(SCKL)
t
t
h(SS)
f
t
t
t
t
dis(SO)
t
t
t
r(SCK)
f(SCK)
t
SCK =
su(MI)
t
h(MO)
su(SI)
a(SO)
h(SO)
v(MO)
MISO
MOSI
v(SO)
h(MI)
c(SCK)
h(SI)
, and T
SS
1)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
1)
OUTPUT
INPUT
INPUT
A
SPI clock frequency
SPI clock rise and fall time
SS setup time
SS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
unless otherwise specified.
CPU
see note 2
. For example, if f
Parameter
t
a(SO)
t
su(SS)
t
su(SI)
4)
CPU
t
t
MSB IN
w(SCKH)
w(SCKL)
MSB OUT
= 8MHz, then T
Master
f
Slave
f
Slave
Slave
Master
Slave
Master
Slave
Master
Slave
Slave
Slave
Slave (after enable edge)
Master (after enable edge)
CPU
CPU
t
t
h(SI)
c(SCK)
=8MHz
=8MHz
Conditions
t
DD
v(SO)
DD
,
CPU
BIT6 OUT
and 0.7xV
= 1/ f
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).
3)
CPU
DD
BIT1 IN
= 125ns and t
.
(4 x T
t
h(SO)
f
CPU
0.0625
CPU
Min
120
100
100
100
100
100
90
/128 =
0
0
0
0
see I/O port pin description
) +150
t
t
r(SCK)
f(SCK)
SU(SS)
LSB IN
= 550ns
LSB OUT
t
h(SS)
f
f
CPU
CPU
Max
120
240
120
120
2
4
/4 =
/2 =
ST7LITE2
t
dis(SO)
113/133
Unit
note 2
MHz
see
ns