ST7LITE25F2 STMicroelectronics, ST7LITE25F2 Datasheet - Page 27

• Manufacturer Part Number: ST7LITE25F2
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7LITE25F2

• 8 Kbytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55˚C.
• Clock Sources: Internal 1% RC oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt

7.5 RESET SEQUENCE MANAGER (RSM)
7.5.1 Introduction
The reset sequence manager includes three RE-
SET sources as shown in
■
■
■
Note: A reset can also be triggered following the
detection of an illegal opcode or prebyte code. Re-
fer to
These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of 3 phases
as shown in
■
■
■
The 256 or 4096 CPU clock cycle delay allows the
oscillator to stabilise and ensures that recovery
has taken place from the Reset state. The shorter
or longer clock cycle delay is automatically select-
ed depending on the clock source chosen by op-
tion byte:
Figure 15. Reset Block Diagram
Note 1: See “Illegal Opcode Reset” on page 88. for more details on illegal opcode reset conditions.
Internal RC Oscillator
External clock (connected to CLKIN pin)
External Crystal/Ceramic Oscillator
(connected to OSC1/OSC2 pins)
External RESET source pulse
Internal LVD RESET (Low Voltage Detection)
Internal WATCHDOG RESET
Active Phase depending on the RESET source
256 or 4096 CPU clock cycle delay (see table
below)
RESET vector fetch
RESET
section 12.2.1 on page 88
Clock Source
Figure
14:
V
Figure
DD
R
ON
for further details.
15:
cycle delay
CPU clock
Filter
4096
256
256
GENERATOR
PULSE
The RESET vector fetch phase duration is 2 clock
cycles.
If the PLL is enabled by option byte, it outputs the
clock after an additional delay of t
Figure
Figure 14. RESET Sequence Phases
7.5.2 Asynchronous External RESET pin
The RESET pin is both an input and an open-drain
output with integrated R
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
Electrical Characteristic section for more details.
A RESET signal originating from an external
source must have a duration of at least t
order to be recognized (see
tection is asynchronous and therefore the MCU
can enter reset state even in HALT mode.
Active Phase
12).
256 or 4096 CLOCK CYCLES
INTERNAL RESET
RESET
WATCHDOG RESET
ILLEGAL OPCODE RESET
LVD RESET
ON
weak pull-up resistor.
Figure
INTERNAL
RESET
STARTUP
16). This de-
ST7LITE2
VECTOR
h(RSTL)in
FETCH
27/133
(see
1)
in
1