ST7LITE25F2 STMicroelectronics, ST7LITE25F2 Datasheet - Page 123

• Manufacturer Part Number: ST7LITE25F2
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7LITE25F2

• 8 Kbytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55˚C.
• Clock Sources: Internal 1% RC oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt

OPTION BYTES (Cont’d)
OPTION BYTE 1
OPT7 = PLLx4x8 PLL Factor selection.
0: PLLx4
1: PLLx8
OPT6 = PLLOFF PLL disable.
0: PLL enabled
1: PLL disabled (by-passed)
OPT5 = PLL32OFF 32MHz PLL disable.
0: PLL32 enabled
1: PLL32 disabled (by-passed)
OPT4 = OSC RC Oscillator selection
0: RC oscillator on
1: RC oscillator off
Notes:
1. 1% RC oscillator available on ST7LITE25 and
ST7LITE29 devices only
2. If the RC oscillator is selected, then to improve
clock stability and frequency accuracy, it is recom-
mended to place a decoupling capacitor, typically
100nF, between the V
possible to the ST7 device.
Table 24. List of valid option combinations
Note 1: Configuration available on ST7LITE25 and ST7LITE29 devices only
Note: see Clock Management Block diagram in
V
2.4V - 3.3V
3.3V - 5.5V
DD
range
Operating conditions
Clock Source
Internal RC 1%
External clock or oscillator
(depending on OPT6:4 selec-
tion)
Internal RC 1%
External clock or oscillator
(depending on OPT6:4 selec-
tion)
DD
and V
1)
1)
SS
pins as close as
PLL
off
x4
x8
off
x4
x8
off
x4
x8
off
x4
x8
Figure 13
OPT3:2 = LVD[1:0] Low voltage detection selec-
tion
These option bits enable the LVD block with a se-
lected threshold as shown in
Table 23. LVD Threshold Configuration
OPT1 = WDG SW Hardware or Software
Watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
OPT0 = WDG HALT Watchdog Reset on Halt
This option bit determines if a RESET is generated
when entering HALT mode while the Watchdog is
active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
Typ f
0.7MHz @3V
2.8MHz @3V
-
0-4MHz
4MHz
-
1MHz @5V
-
8MHz @5V
0-8MHz
-
8 MHz
LVD Off
Highest Voltage Threshold (∼4.1V)
Medium Voltage Threshold (∼3.5V)
Lowest Voltage Threshold (∼2.8V)
CPU
Configuration
OSC
0
0
1
1
0
0
1
1
-
-
-
-
Option Bits
PLLOFF
Table
1
0
1
0
1
0
1
0
-
-
-
-
23.
ST7LITE2
LVD1 LVD0
PLLx4x8
1
1
0
0
123/133
1
0
1
0
1
1
1
1
-
-
-
-
1
0
1
0