ST72215G2 STMicroelectronics, ST72215G2 Datasheet
ST72215G2
Specifications of ST72215G2
Related parts for ST72215G2
ST72215G2 Summary of contents
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... Instruction Set – 8-bit data manipulation – 63 basic instructions – 17 main addressing modes – unsigned multiply instruction – True bit manipulation Development Tools – Full hardware/software development package ST72215G2 ST72254G1 8K 4K 256 (128) Watchdog timer, Watchdog timer, Two 16-bit timers, ...
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INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx 1 INTRODUCTION The ST72104G, ST72215G, ST72216G and ST72254G devices are members of the ST7 mi- crocontroller family. They can be grouped as fol- lows: – ST72254G devices are designed for mid-range applications with ADC and I²C ...
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PIN DESCRIPTION Figure 2. 28-Pin SO Package Pinout ISPCLK/SCK/PB6 ISPDATA/MISO/PB5 OCMP2_A/PB3 ICAP2_A/PB2 OCMP1_A/PB1 ICAP1_A/PB0 AIN5/EXTCLK_A/PC5 AIN4/OCMP2_B/PC4 AIN3/ICAP2_B/PC3 Figure 3. 32-Pin SDIP Package Pinout ISPCLK/SCK/PB6 ISPDATA/MISO/PB5 OCMP2_A/PB3 ICAP2_A/PB2 OCMP1_A/PB1 ICAP1_A/PB0 AIN5/EXTCLK_A/PC5 AIN4/OCMP2_B/PC4 AIN3/ICAP2_B/PC3 ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx RESET 1 28 ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx PIN DESCRIPTION (Cont’d) For external pin connection guidelines, refer to 96. Legend / Abbreviations for Type input output supply Input level Dedicated analog input In/Output level ...
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Pin n° Pin Name 18 16 PC1/OCMP1_B/AIN1 I PC0/ICAP1_B/AIN0 I PA7 I PA6 /SDAI I PA5 I PA4 /SCLI I ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx 3 REGISTER & MEMORY MAP As shown in the Figure 4, the MCU is capable of addressing 64K bytes of memories and I/O regis- ters. The available memory locations consist of 128 bytes of register location, ...
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Table 2. Hardware Register Map Register Address Block 0000h PCDR 0001h Port C PCDDR 0002h PCOR 0003h 0004h PBDR 0005h Port B PBDDR 0006h PBOR 0007h 0008h PADR 0009h Port A PADDR 000Ah PAOR 000Bh to 001Fh 0020h MISCR1 0021h ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx Register Address Block 0031h TACR2 0032h TACR1 0033h TASR 0034h TAIC1HR 0035h TAIC1LR 0036h TAOC1HR 0037h TAOC1LR 0038h TIMER A TACHR 0039h TACLR 003Ah TAACHR 003Bh TAACLR 003Ch TAIC2HR 003Dh TAIC2LR 003Eh TAOC2HR 003Fh TAOC2LR 0040h ...
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FLASH PROGRAM MEMORY 4.1 INTRODUCTION FLASH devices have a single voltage non-volatile FLASH memory that may be programmed in-situ (or plugged in a programming tool byte-by- byte basis. 4.2 MAIN FEATURES Remote In-Situ Programming (ISP) mode ■ ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx 5 CENTRAL PROCESSING UNIT 5.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 5.2 MAIN FEATURES 63 basic instructions ■ Fast 8-bit by 8-bit multiply ■ ...
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CPU REGISTERS (cont’d) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx The 8-bit Condition Code register contains the in- terrupt mask and four flags representative of the result of the instruction just executed. This ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx CENTRAL PROCESSING UNIT (Cont’d) Stack Pointer (SP) Read/Write Reset Value: 01 7Fh SP6 SP5 SP4 SP3 The Stack Pointer is a 16-bit register which is al- ways pointing ...
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SUPPLY, RESET AND CLOCK MANAGEMENT The ST72104G, ST72215G, ST72216G and ST72254G microcontrollers include a range of util- ity features for securing the application in critical situations (for example in case of a power brown- out), and reducing the number ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx 6.1 LOW VOLTAGE DETECTOR (LVD) To allow the integration of power management features in the application, the Low Voltage Detec- tor function (LVD) generates a static reset when the V supply voltage is below a V ...
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RESET SEQUENCE MANAGER (RSM) 6.2.1 Introduction The reset sequence manager includes three RE- SET sources as shown in Figure External RESET source pulse ■ Internal LVD RESET (Low Voltage Detection) ■ Internal WATCHDOG RESET ■ These sources act on ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx RESET SEQUENCE MANAGER (Cont’d) 6.2.2 Asynchronous External RESET pin The RESET pin is both an input and an open-drain output with integrated R weak pull-up resistor. ON This pull-up has no fixed value but varies in ...
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MULTI-OSCILLATOR (MO) The main clock of the ST7 can be generated by four different source types coming from the multi- oscillator block: an external source ■ 4 crystal or ceramic resonator oscillators ■ an external RC oscillator ■ an ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx 6.4 CLOCK SECURITY SYSTEM (CSS) The Clock Security System (CSS) protects the ST7 against main clock problems. To allow the in- tegration of the security features in the applica- tions based on a clock ...
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CLOCK RESET AND SUPPLY REGISTER DESCRIPTION (CRSR) Read / Write Reset Value: 000x 000x (XXh) 7 LVD Bit 7:5 = Reserved, always read as 0. Bit 4 = LVDRF LVD reset flag This bit ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx 6.6 MAIN CLOCK CONTROLLER (MCC) The Main Clock Controller (MCC) supplies the clock for the ST7 CPU and its internal peripherals. It allows SLOW power saving mode to be man- aged by the application. All functions ...
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INTERRUPTS The ST7 core may be interrupted by one of two dif- ferent methods: maskable hardware interrupts as listed in the Interrupt Mapping Table and a non- maskable software interrupt (TRAP). The Interrupt processing flowchart is shown in The ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx INTERRUPTS (Cont’d) Figure 15. Interrupt Processing Flowchart FROM RESET EXECUTE INSTRUCTION Table 5. Interrupt Mapping Source N° Block RESET Reset TRAP Software Interrupt 0 ei0 External Interrupt Port A7..0 (C5..0 1 ei1 External Interrupt Port B7..0 ...
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POWER SAVING MODES 8.1 INTRODUCTION To give a large measure of flexibility to the applica- tion in terms of power consumption, three main power saving modes are implemented in the ST7 (see Figure 16). After a RESET the normal ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx POWER SAVING MODES (Cont’d) 8.3 WAIT MODE WAIT mode places the MCU in a low power con- sumption mode by stopping the CPU. This power saving mode is selected by calling the “WFI” ST7 software instruction. ...
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POWER SAVING MODES (Cont’d) 8.4 HALT MODE The HALT mode is the lowest power consumption mode of the MCU entered by executing the ST7 HALT instruction (see Figure The MCU can exit HALT mode on reception of ei- ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx 9 I/O PORTS 9.1 INTRODUCTION The I/O ports offer different functional modes: – transfer of data through digital inputs and outputs and for specific pins: – external interrupt generation – alternate signal input/output for the on-chip ...
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I/O PORTS (Cont’d) Figure 21. I/O Port General Block Diagram ALTERNATE REGISTER OUTPUT ACCESS ALTERNATE ENABLE DR DDR OR If implemented OR SEL DDR SEL DR SEL 1 0 EXTERNAL INTERRUPT SOURCE ( POLARITY SELECTION Table 6. I/O ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx I/O PORTS (Cont’d) Table 7. I/O Port Configurations NOT IMPLEMENTED IN V TRUE OPEN DRAIN I/O PORTS PAD NOT IMPLEMENTED IN TRUE OPEN DRAIN V I/O PORTS PAD NOT IMPLEMENTED IN TRUE OPEN DRAIN V I/O ...
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I/O PORTS (Cont’d) CAUTION: The alternate function must not be ac- tivated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. Analog alternate function When the pin is used as an ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx I/O PORTS (Cont’d) 9.4 LOW POWER MODES Mode Description No effect on I/O ports. External interrupts WAIT cause the device to exit from WAIT mode. No effect on I/O ports. External interrupts HALT cause the device ...
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I/O PORTS (Cont’d) Table 9. I/O Port Register Map and Reset Values Address Register 7 Label (Hex.) Reset Value of all I/O port registers 0000h PCDR 0001h PCDDR MSB 0002h PCOR 0004h PBDR 0005h PBDDR MSB 0006h PBOR 0008h PADR ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx 10 MISCELLANEOUS REGISTERS The miscellaneous registers allow control over several different features such as the external in- terrupts or the I/O alternate functions. 10.1 I/O PORT INTERRUPT SENSITIVITY The external interrupt sensitivity is controlled by the ...
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MISCELLANEOUS REGISTERS (Cont’d) 10.3 MISCELLANEOUS REGISTER DESCRIPTION MISCELLANEOUS REGISTER 1 (MISCR1) Read / Write Reset Value: 0000 0000 (00h) 7 IS11 IS10 MCO IS01 IS00 Bit 7:6 = IS1[1:0] ei1 sensitivity The interrupt sensitivity, defined using the IS1[1:0] bits, is ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx MISCELLANEOUS REGISTERS (Cont’d) MISCELLANEOUS REGISTER 2 (MISCR2) Read / Write Reset Value: 0000 0000 (00h MOD SOD SSM Bit 7:4 = Reserved always read as 0 Bit 3 = MOD SPI ...
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ON-CHIP PERIPHERALS 11.1 WATCHDOG TIMER (WDG) 11.1.1 Introduction The Watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx WATCHDOG TIMER (Cont’d) Table 11. Watchdog Timing (f CR Register initial value Max FFh Min C0h Notes: Following a reset, the watchdog is disa- bled. Once activated it cannot be disabled, except by a reset. The ...
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WATCHDOG TIMER (Cont’d) Table 12. Watchdog Timer Register Map and Reset Values Address Register 7 Label (Hex.) WDGCR WDGA 0024h Reset Value 0 ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx 11.2 16-BIT TIMER 11.2.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including measuring the pulse lengths two ...
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TIMER (Cont’d) Figure 26. Timer Block Diagram f CPU 8 high EXEDG 1/2 COUNTER 1/4 REGISTER 1/8 ALTERNATE EXTCLK pin COUNTER REGISTER CC[1:0] OVERFLOW DETECT CIRCUIT ICF1 OCF1 TOF ICF2 ICIE OCIE TOIE FOLV2 (See note) TIMER INTERRUPT ST72104Gx, ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx 16-BIT TIMER (Cont’d) 16-bit Read Sequence: (from either the Counter Register or the Alternate Counter Register). Beginning of the sequence Read MS Byte At t0 Other instructions Returns the buffered Read At t0 +∆t LS Byte ...
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TIMER (Cont’d) Figure 27. Counter Timing Diagram, internal clock divided by 2 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) Figure 28. Counter Timing Diagram, internal clock divided by 4 CPU CLOCK INTERNAL RESET TIMER ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx 16-BIT TIMER (Cont’d) 11.2.3.3 Input Capture In this section, the index, i, may because there are 2 input capture functions in the 16-bit timer. The two input capture 16-bit registers (IC1R and ...
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TIMER (Cont’d) Figure 30. Input Capture Block Diagram ICAP1 pin EDGE DETECT CIRCUIT2 ICAP2 pin IC2R Register 16-BIT 16-BIT FREE RUNNING COUNTER Figure 31. Input Capture Timing Diagram TIMER CLOCK COUNTER REGISTER ICAPi PIN ICAPi FLAG ICAPi REGISTER Note: ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx 16-BIT TIMER (Cont’d) 11.2.3.4 Output Compare In this section, the index, i, may because there are 2 output compare functions in the 16-bit timer. This function can be used to control an ...
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TIMER (Cont’d) Notes: 1. After a processor write cycle to the OCiHR reg- ister, the output compare function is inhibited until the OCiLR register is also written the OCiE bit is not set, the OCMPi pin is ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx 16-BIT TIMER (Cont’d) Figure 33. Output Compare Timing Diagram, f INTERNAL CPU CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi = 1) Figure 34. Output Compare Timing Diagram, ...
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TIMER (Cont’d) 11.2.3.5 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The One Pulse mode uses the Input ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx 16-BIT TIMER (Cont’d) Figure 35. One Pulse Mode Timing Example COUNTER ICAP1 OCMP1 Note: IEDG1 = 1, OC1R = 2ED0h, OLVL1 = 0, OLVL2 = 1 Figure 36. Pulse Width Modulation Mode Timing Example COUNTER 34E2 ...
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TIMER (Cont’d) 11.2.3.6 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. The Pulse Width Modulation mode ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx 16-BIT TIMER (Cont’d) 11.2.4 Low Power Modes Mode No effect on 16-bit Timer. WAIT Timer interrupts cause the device to exit from WAIT mode. 16-bit Timer registers are frozen. In HALT mode, the counter stops counting ...
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TIMER (Cont’d) 11.2.7 Register Description Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the al- ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx 16-BIT TIMER (Cont’d) CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00h) 7 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG Bit 7 = OC1E Output Compare 1 Pin Enable. This bit is used only ...
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TIMER (Cont’d) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) The three least significant bits are not used. 7 ICF1 OCF1 TOF ICF2 OCF2 Bit 7 = ICF1 Input Capture Flag input capture (reset ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx 16-BIT TIMER (Cont’d) OUTPUT COMPARE 2 (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 7 MSB OUTPUT ...
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TIMER (Cont’d) Table 14. 16-Bit Timer Register Map and Reset Values Address Register 7 Label (Hex.) Timer A: 32 CR1 ICIE Timer B: 42 Reset Value Timer A: 31 CR2 OC1E Timer B: 41 Reset Value Timer A: 33 ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx 11.3 SERIAL PERIPHERAL INTERFACE (SPI) 11.3.1 Introduction The Serial Peripheral Interface (SPI) allows full- duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) Figure 38. Serial Peripheral Interface Block Diagram Read Read Buffer MOSI MISO 8-Bit Shift Register SCK SS ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx Internal Bus DR Write MASTER CONTROL SERIAL CLOCK GENERATOR MODF SPIF WCOL - - - ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.4 Functional Description Figure 1 shows the serial peripheral interface (SPI) block diagram. This interface contains three dedicated registers: – A Control Register (CR) – A Status Register (SR) – A Data ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.4.2 Slave Configuration In slave configuration, the serial clock is received on the SCK pin from the master device. The value of the SPR0 & SPR1 bits is not used for the data transfer. Procedure – ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.4.3 Data Transfer Format During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). The serial clock is used to syn- chronize the data transfer during ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) Figure 40. Data Clock Timing Diagram SCLK (with CPOL = 1) SCLK (with CPOL = 0) MSBit MISO (from master) MSBit MOSI (from slave) SS (to slave) CAPTURE STROBE CPOL = 1 CPOL = 0 MSBit ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.4.4 Write Collision Error A write collision occurs when the software tries to write to the DR register while a data transfer is tak- ing place with an external device. When this ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.4.5 Master Mode Fault Master mode fault occurs when the master device has its SS pin pulled low, then the MODF bit is set. Master mode fault affects the SPI peripheral in the following ways: – ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.4.7 Single Master and Multimaster Configurations There are two types of SPI systems: – Single Master System – Multimaster System Single Master System A typical single master system may be configured, using ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.5 Low Power Modes Mode No effect on SPI. WAIT SPI interrupt events cause the device to exit from WAIT mode. SPI registers are frozen. HALT In HALT mode, the SPI is inactive. SPI operation resumes ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.7 Register Description CONTROL REGISTER (CR) Read/Write Reset Value: 0000xxxx (0xh) 7 SPIE SPE SPR2 MSTR CPOL Bit 7 = SPIE Serial peripheral interrupt enable. This bit is set and cleared by ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) 7 SPIF WCOL - MODF Bit 7 = SPIF Serial Peripheral data transfer flag. This bit is set by hardware when a transfer has been completed. ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx SERIAL PERIPHERAL INTERFACE (Cont’d) Table 16. SPI Register Map and Reset Values Address Register 7 Label (Hex.) SPIDR MSB 0021h Reset Value SPICR SPIE 0022h Reset Value SPISR SPIF 0023h Reset Value 72/141 ...
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I C BUS INTERFACE (I2C) 11.4.1 Introduction 2 The I C Bus Interface serves as an interface be- tween the microcontroller and the serial I provides both multimaster and slave functions, 2 and controls all I C bus-specific ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx BUS INTERFACE (Cont’d) Acknowledge may be enabled and disabled by software. 2 The I C interface address and/or general call ad- dress can be selected by software. 2 The speed of the I ...
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I C BUS INTERFACE (Cont’d) 11.4.4 Functional Description Refer to the CR, SR1 and SR2 registers in 0.1.7. for the bit definitions default the I C interface operates in Slave mode (M/SL bit is cleared) except when ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx to correctly handle a second interrupt during the 9th pulse of a transmitted byte. Note: In both cases, SCL line is not held low; how- ever, the SDA line can remain low if the last bits ...
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I C BUS INTERFACE (Cont’d) Master Transmitter Following the address transmission and after SR1 register has been read, the master sends bytes from the DR register to the SDA line via the inter- nal shift register. The master waits ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx BUS INTERFACE (Cont’d) Figure 45. Transfer Sequencing 7-bit Slave receiver: S Address A Data1 EV1 7-bit Slave transmitter: S Address A Data1 EV1 EV3 7-bit Master receiver: S Address A EV5 EV6 7-bit ...
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I C BUS INTERFACE (Cont’d) 11.4.5 Low Power Modes Mode 2 No effect interface. WAIT interrupts cause the device to exit from WAIT mode registers are frozen. 2 HALT In ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx BUS INTERFACE (Cont’d) 11.4.7 Register Description CONTROL REGISTER (CR) Read / Write Reset Value: 0000 0000 (00h ENGC START ACK Bit 7:6 = Reserved. Forced to ...
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I C BUS INTERFACE (Cont’ STATUS REGISTER 1 (SR1) Read Only Reset Value: 0000 0000 (00h) 7 EVF ADD10 TRA BUSY BTF Bit 7 = EVF Event flag. This bit is set by hardware as soon ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx BUS INTERFACE (Cont’d) Bit 1 = M/SL Master/Slave. This bit is set by hardware as soon as the interface is in Master mode (writing START=1 cleared by hardware after detecting a ...
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I C BUS INTERFACE (Cont’ CLOCK CONTROL REGISTER (CCR) Read / Write Reset Value: 0000 0000 (00h) 7 FM/SM CC6 CC5 CC4 CC3 Bit 7 = FM/SM Fast/Standard I This bit is set and cleared by ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx BUS INTERFACE (Cont’ OWN ADDRESS REGISTER (OAR1) Read / Write Reset Value: 0000 0000 (00h) 7 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 7-bit Addressing Mode Bit 7:1 = ...
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I²C BUS INTERFACE (Cont’d) 2 Table 17 Register Map and Reset Values Address Register 7 Label (Hex.) I2CCR 0028h Reset Value 0 I2CSR1 EVF 0029h Reset Value 0 I2CSR2 002Ah Reset Value 0 I2CCCR FM/SM 02Bh Reset Value ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx 11.5 8-BIT A/D CONVERTER (ADC) 11.5.1 Introduction The on-chip Analog to Digital Converter (ADC) pe- ripheral is a 8-bit, successive approximation con- verter with internal sample and hold circuitry. This peripheral has multiplexed ...
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A/D CONVERTER (ADC) (Cont’d) 11.5.3.2 Digital A/D Conversion Result The conversion is monotonic, meaning that the re- sult never decreases if the analog input does not and never increases if the analog input does not. If the input voltage ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx 8-BIT A/D CONVERTER (ADC) (Cont’d) 11.5.6 Register Description CONTROL/STATUS REGISTER (CSR) Read / Write Reset Value: 0000 0000 (00h) 7 COCO 0 ADON 0 CH3 Bit 7 = COCO Conversion Complete This bit is set by ...
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A/D CONVERTER (ADC) (Cont’d) Table 18. ADC Register Map and Reset Values Address Register 7 Label (Hex.) ADCDR D7 0070h Reset Value 0 ADCCSR COCO 0071h Reset Value 0 ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx 12 INSTRUCTION SET 12.1 ST7 ADDRESSING MODES The ST7 Core features 17 different addressing modes which can be classified in 7 main groups: Addressing Mode Example Inherent nop Immediate ld A,#$55 Direct ld A,$55 Indexed ld ...
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ST7 ADDRESSING MODES (Cont’d) 12.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required informa- tion for the CPU to process the operation. Inherent Instruction NOP No operation TRAP S/W Interrupt Wait For ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx ST7 ADDRESSING MODES (Cont’d) 12.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the un- signed addition ...
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INSTRUCTION GROUPS The ST 7 family devices use an Instruction Set consisting of 63 instructions. The instructions may Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and Branch Arithmetic operations Shift ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx INSTRUCTION GROUPS (Cont’d) Mnemo Description ADC Add with Carry ADD Addition AND Logical And BCP Bit compare A, Memory BRES Bit Reset BSET Bit Set BTJF Jump if bit is false (0) BTJT Jump if bit ...
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INSTRUCTION GROUPS (Cont’d) Mnemo Description JRULE Jump Load MUL Multiply NEG Negate (2's compl) NOP No Operation OR OR operation POP Pop from the Stack PUSH Push onto the Stack RCF Reset carry ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx 13 ELECTRICAL CHARACTERISTICS 13.1 PARAMETER CONDITIONS Unless otherwise specified, all voltages are re- ferred 13.1.1 Minimum and Maximum values Unless otherwise specified the minimum and max- imum values are guaranteed in the ...
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ABSOLUTE MAXIMUM RATINGS Stresses above those listed as “absolute maxi- mum ratings” may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device under these condi- 13.2.1 Voltage Characteristics Symbol ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx 13.3 OPERATING CONDITIONS 13.3.1 General Operating Conditions Symbol Parameter V Supply voltage DD f External clock frequency OSC T Ambient temperature range A Figure 51. f Maximum Operating Frequency Versus V OSC f [MHz] OSC 16 ...
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OPERATING CONDITIONS (Cont’d) Figure 52. f Maximum Operating Frequency Versus V OSC f [MHz] OSC 16 FUNCTIONALITY NOT GUARANTEED 12 IN THIS AREA 2.5 Notes: 1. Guaranteed by construction. A/D operation and resonator oscillator start-up are ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx OPERATING CONDITIONS (Cont’d) 13.3.2 Operating Conditions with Low Voltage Detector (LVD) Subject to general operating conditions for V Symbol Parameter Reset release threshold V IT+ (V rise) DD Reset generation threshold V IT- (V fall) DD ...
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FUNCTIONAL OPERATING CONDITIONS (Cont’d) Figure 56. High LVD Threshold Versus V f [MHz] OSC 16 DEVICE UNDER RESET IN THIS AREA 8 0 2.5 Figure 57. Medium LVD Threshold Versus V f [MHz] OSC 16 DEVICE UNDER RESET IN THIS ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx 13.4 SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for the ST7 functional operating modes over tempera- ture range does not take into account the clock source current consumption. To get the total de- Symbol Parameter ...
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SUPPLY CURRENT CHARACTERISTICS (Cont’d) 13.4.2 WAIT and SLOW WAIT Modes Symbol Parameter Supply current in WAIT mode (see Figure 61) Supply current in SLOW WAIT mode (see Figure 62 Supply current in WAIT mode (see Figure 61) Supply ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx SUPPLY CURRENT CHARACTERISTICS (Cont’d) 13.4.3 HALT Mode Symbol Parameter I Supply current in HALT mode DD 13.4.4 Supply and Clock Managers The previous current consumption specified for the ST7 functional operating modes over tempera- ture range ...
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CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for V 13.5.1 General Timings Symbol Parameter t Instruction cycle time c(INST) Interrupt reaction time t = ∆t v(IT v(IT) c(INST) 13.5.2 External Clock Source Symbol Parameter ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx CLOCK AND TIMING CHARACTERISTICS (Cont’d) 13.5.3 Crystal and Ceramic Resonator Oscillators The ST7 internal clock can be supplied with four different Crystal/Ceramic resonator oscillators. All the information given in this paragraph are based on characterization results ...
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CLOCK AND TIMING CHARACTERISTICS (Cont’d) 13.5.3.2 Typical Ceramic Resonators Symbol t Ceramic resonator start-up time SU(osc the typical oscillator start-up time measured between V SU(OSC) quick V ramp-up from (<50µs). DD Table 21. Typical Ceramic ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx CLOCK AND TIMING CHARACTERISTICS (Cont’d) Figure 65. Typical Application with Ceramic Resonator WHEN RESONATOR WITH INTEGRATED CAPACITORS Notes: 1. Resonator characteristics given by the ceramic resonator manufacturer the typical ...
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CLOCK AND TIMING CHARACTERISTICS (Cont’d) Table 22. Ceramic Resonator Frequency Correlation Factor Option 1) Byte Resonator Config. CSB1000J LP CSTS0200MG06 CSTCC2.00MG0H6 CSTS0200MG06 CSTCC2.00MG0H6 MP CSTS0400MG06 CSTS0400MGA06 CSTCC4.00MG0H6 CSTS0200MG06 CSTCC2.00MG0H6 CSTS0400MG06 MS CSTS0400MGA06 CSTCC4.00MG0H6 CSTS0200MG06 Notes: 1. See Table 21 for ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx CLOCK CHARACTERISTICS (Cont’d) 13.5.4 RC Oscillators The ST7 internal clock can be supplied with an RC oscillator. This oscillator can be used with internal Symbol Parameter Internal RC oscillator frequency f OSC External RC oscillator frequency ...
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CLOCK CHARACTERISTICS (Cont’d) 13.5.5 Clock Security System (CSS) Symbol Parameter f Safe Oscillator Frequency SFOSC f Glitch Filtered Frequency GFOSC Figure 69. Typical Safe Oscillator Frequencies fos c [kHz] -40°C 400 + 25°C 350 300 250 200 3.2 VDD [V] ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx 13.6 MEMORY CHARACTERISTICS Subject to general operating conditions for V 13.6.1 RAM and Hardware Registers Symbol Parameter V Data retention mode RM 13.6.2 FLASH Program Memory Symbol Parameter T Programming temperature range A(prog) Programming time for ...
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EMC CHARACTERISTICS Susceptibility tests are performed on a sample ba- sis during product characterization. 13.7.1 Functional EMS (Electro Magnetic Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx EMC CHARACTERISTICS (Cont’d) 13.7.2 Absolute Electrical Sensitivity Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For ...
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... GENERATOR Notes: 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec- ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard). 2. Schaffner NSG435 with a pointed test finger. ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx EMC CHARACTERISTICS (Cont’d) 13.7.3 ESD Pin Protection Strategy To protect an integrated circuit against Electro- Static Discharge the stress must be controlled to prevent degradation or destruction of the circuit el- ements. The stress generally affects ...
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EMC CHARACTERISTICS (Cont’d) True Open Drain Pin Protection The centralized protection (4) is not involved in the discharge of the ESD stresses applied to true open drain pads due to the fact that a P-Buffer and diode to V are ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx 13.8 I/O PORT PIN CHARACTERISTICS 13.8.1 General Characteristics Subject to general operating conditions for V Symbol Parameter V Input low level voltage IL V Input high level voltage IH V Schmitt trigger voltage hysteresis hys I ...
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I/O PORT PIN CHARACTERISTICS (Cont’d) 13.8.2 Output Driving Current Subject to general operating conditions for V Symbol Parameter Output low level voltage for a standard I/O pin when 8 pins are sunk at same time (see Figure 80 and Figure ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx I/O PORT PIN CHARACTERISTICS (Cont’d) Figure 83. Typical V vs Vol [ o=2mA 0.5 0.4 5 0.4 0.3 5 0.3 0.2 5 0.2 3.2 3 [V] Figure ...
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CONTROL PIN CHARACTERISTICS 13.9.1 Asynchronous RESET Pin Subject to general operating conditions for V Symbol Parameter V Input low level voltage IL V Input high level voltage IH V Schmitt trigger voltage hysteresis hys Output low level voltage V ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx CONTROL PIN CHARACTERISTICS (Cont’d) Figure 87. Typical I vs [µA] Ta=-40°C 200 Ta=25°C 150 100 50 0 3.2 3 [V] Figure 89. Typical V vs ...
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CONTROL PIN CHARACTERISTICS (Cont’d) 13.9.2 ISPSEL Pin Subject to general operating conditions for V Symbol Parameter V Input low level voltage IL V Input high level voltage IH I Input leakage current L Figure 90. Two typical Applications with ISPSEL ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx 13.10 TIMER PERIPHERAL CHARACTERISTICS Subject to general operating conditions for and T unless otherwise specified. OSC A 13.10.1 Watchdog Timer Symbol Parameter t Watchdog time-out duration w(WDG) 13.10.2 16-Bit Timer Symbol Parameter t ...
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COMMUNICATION INTERFACE CHARACTERISTICS 13.11.1 SPI - Serial Peripheral Interface Subject to general operating conditions for and T unless otherwise specified. OSC A Symbol Parameter f SCK SPI clock frequency 1/t c(SCK) t r(SCK) SPI clock rise ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) Figure 92. SPI Slave Timing Diagram with CPHA=1 SS INPUT t su(SS) CPHA=0 CPOL=0 CPHA=0 CPOL=1 t w(SCKH) t a(SO) t w(SCKL) see MISO OUTPUT HZ note 2 t su(SI) MOSI INPUT ...
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COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) 2 13.11 Inter IC Control Interface Subject to general operating conditions for and T unless otherwise specified. OSC A Symbol Parameter t SCL clock low time w(SCLL) t SCL clock ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx 13.12 8-BIT ADC CHARACTERISTICS Subject to general operating conditions for V Symbol Parameter f ADC clock frequency ADC V Conversion range voltage AIN R External input resistor AIN C Internal sample and hold capacitor ADC t ...
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ADC CHARACTERISTICS (Cont’d) ADC Accuracy Symbol Parameter Total unadjusted error Offset error Gain Error Differential linearity error Integral linearity error L Figure 96. ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx 14 PACKAGE CHARACTERISTICS 14.1 PACKAGE MECHANICAL DATA Figure 97. 32-Pin Shrink Plastic Dual In Line Package Figure 98. 28-Pin Plastic Small Outline Package, 300-mil Width 130/141 E See Lead ...
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THERMAL CHARACTERISTICS Symbol Package thermal resistance (junction to ambient) R thJA P Power dissipation D T Maximum junction temperature Jmax Notes: 1. The power dissipation is obtained from the formula P and P is the port power dissipation determined ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx 14.3 SOLDERING INFORMATION In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level in- terconnect. The category of second level intercon- nect is marked on the ...
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DEVICE CONFIGURATION AND ORDERING INFORMATION Each device is available for production in user pro- grammable versions (FLASH) as well as in factory coded versions (ROM). FLASH devices are shipped to customers with a default content (FFh), while ROM factory ...
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... B= Plastic DIP M= Plastic SOIC ST72104G1, ST72104G2, ST72215G2, ST72216G1, ST72254G1, ST72254G2 +70 ° -10 to +85°C 6= -40 to +85 °C 7= -40 to +105° -40 to +125 °C B= Plastic DIP ...
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... ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx MICROCONTROLLER OPTION LIST [ ] ST72104G1 (4KB ST72215G2 (4KB ST72104G2 (8KB ST72216G1 (8KB SO28 [ ] Tape & ...
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... ST7 HDS2 Emulator features including trace/ logic analyzer ST7 Programming Board No Table 27. Dedicated STMicroelectronics Development Tools Supported Products ST72254G1, ST72C254G1 ST72254G2, ST72C254G2 ST72215G2, ST72C215G2 ST72216G1, ST72C216G1 ST72104G1, ST72C104G1, ST72104G2, ST72C104G2 Note: 1. In-Situ Programming (ISP) interface for FLASH devices. 136/141 STMicroelectronics Tools ...
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DEVELOPMENT TOOLS (Cont’d) 15.3.1 PACKAGE/SOCKET FOOTPRINT PROPOSAL Table 28. Suggested List of SDIP32 Socket Types Package / Probe SDIP32 TEXTOOL EMU PROBE Table 29. Suggested List of SO28 Socket Types Package / Probe ENPLAS SO28 YAMAICHI EMU PROBE Adapter from ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx 15.4 ST7 APPLICATION NOTES IDENTIFICATION EXAMPLE DRIVERS AN 969 SCI COMMUNICATION BETWEEN ST7 AND PC AN 970 SPI COMMUNICATION BETWEEN ST7 AND EEPROM AN 971 I²C COMMUNICATING BETWEEN ST7 AND M24CXX EEPROM AN 972 ST7 SOFTWARE ...
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IDENTIFICATION AN 982 USING ST7 WITH CERAMIC RESONATOR AN1014 HOW TO MINIMIZE THE ST7 POWER CONSUMPTION AN1015 SOFTWARE TECHNIQUES FOR IMPROVING MICROCONTROLLER EMC PERFORMANCE AN1040 MONITORING THE VBUS SIGNAL FOR USB SELF-POWERED DEVICES AN1070 ST7 CHECKSUM SELF-CHECKING CAPABILITY AN1324 CALIBRATING ...
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ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx 16 SUMMARY OF CHANGES Description of the changes between the current release of the specification and the previous one. Rev. Changed Status from Preliminary Data to Datasheet Changed V on page 97 (in the voltage characteristics ...
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... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...