ST72215G2 STMicroelectronics, ST72215G2 Datasheet - Page 34

• Manufacturer Part Number: ST72215G2
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,ADC, 16-BIT TIMERS, SPI, I2C INTERFACES
• Manufacturer: STMicroelectronics

Specifications of ST72215G2

• Emulation Voltage: 5.5 V

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx
I/O PORTS (Cont’d)
9.4 LOW POWER MODES
9.5 INTERRUPTS
The external interrupt event generates an interrupt
if the corresponding configuration is selected with
DDR and OR registers and the I-bit in the CC reg-
ister is reset (RIM instruction).
9.6 REGISTER DESCRIPTION
DATA REGISTER (DR)
Port x Data Register
PxDR with x = A, B or C.
Read / Write
Reset Value: 0000 0000 (00h)
Bit 7:0 = D[7:0] Data register 8 bits.
The DR register has a specific behaviour accord-
ing to the selected input/output configuration. Writ-
ing the DR register is always taken into account
even if the pin is configured as an input; this allows
always having the expected level on the pin when
toggling to output mode. Reading the DR register
returns either the DR register latch content (pin
configured as output) or the digital value applied to
the I/O pin (pin configured as input).
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WAIT
HALT
External interrupt on
selected external
event
D7
Mode
Interrupt Event
7
D6
No effect on I/O ports. External interrupts
cause the device to exit from WAIT mode.
No effect on I/O ports. External interrupts
cause the device to exit from HALT mode.
D5
Event
D4
Flag
-
Description
D3
Control
Enable
DDRx
ORx
Bit
D2
from
Wait
Exit
Yes
D1
from
Exit
Halt
Yes
D0
0
DATA DIRECTION REGISTER (DDR)
Port x Data Direction Register
PxDDR with x = A, B or C.
Read / Write
Reset Value: 0000 0000 (00h)
Bit 7:0 = DD[7:0] Data direction register 8 bits.
The DDR register gives the input/output direction
configuration of the pins. Each bit is set and
cleared by software.
0: Input mode
1: Output mode
OPTION REGISTER (OR)
Port x Option Register
PxOR with x = A, B or C.
Read / Write
Reset Value: 0000 0000 (00h)
Bit 7:0 = O[7:0] Option register 8 bits.
For specific I/O pins, this register is not implement-
ed. In this case the DDR register is enough to se-
lect the I/O pin configuration.
The OR register allows to distinguish: in input
mode if the pull-up with interrupt capability or the
basic pull-up configuration is selected, in output
mode if the push-pull or open drain configuration is
selected.
Each bit is set and cleared by software.
Input mode:
0: Floating input
1: Pull-up input with or without interrupt
Output mode:
0: Output open drain (with P-Buffer deactivated)
1: Output push-pull (when available)
DD7
O7
7
7
DD6
O6
DD5
O5
DD4
O4
DD3
O3
DD2
O2
DD1
O1
DD0
O0
0
0