ST72215G2 STMicroelectronics, ST72215G2 Datasheet - Page 73

• Manufacturer Part Number: ST72215G2
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,ADC, 16-BIT TIMERS, SPI, I2C INTERFACES
• Manufacturer: STMicroelectronics

Specifications of ST72215G2

• Emulation Voltage: 5.5 V

11.4 I
11.4.1 Introduction
The I
tween the microcontroller and the serial I
provides both multimaster and slave functions,
and controls all I
tocol, arbitration and timing. It supports fast I
mode (400kHz).
11.4.2 Main Features
■
■
■
■
■
■
I
■
■
■
■
■
■
■
I
■
■
■
■
■
■
■
11.4.3 General Description
In addition to receiving and transmitting data, this
interface converts it from serial to parallel format
and vice versa, using either an interrupt or polled
Figure 43. I
2
2
C Master Features:
C Slave Features:
Parallel-bus/I
Multi-master capability
7-bit/10-bit Addressing
Transmitter/Receiver flag
End-of-byte transmission flag
Transfer problem detection
Clock generation
I
Arbitration Lost Flag
End of byte transmission flag
Transmitter/Receiver Flag
Start bit detection flag
Start and Stop generation
Stop bit detection
I
Detection of misplaced start or stop condition
Programmable I
Transfer problem detection
End-of-byte transmission flag
Transmitter/Receiver flag
2
2
C bus busy flag
C bus busy flag
2
2
C Bus Interface serves as an interface be-
C BUS INTERFACE (I2C)
2
SCL
SDA
C BUS Protocol
2
C protocol converter
CONDITION
2
C bus-specific sequencing, pro-
2
START
C Address detection
MSB
1
2
C bus. It
2
ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx
2
C
handshake. The interrupts are enabled or disabled
by software. The interface is connected to the I
bus by a data pin (SDAI) and by a clock pin (SCLI).
It can be connected both with a standard I
and a Fast I
ware.
Mode Selection
The interface can operate in the four following
modes:
– Slave transmitter/receiver
– Master transmitter/receiver
By default, it operates in slave mode.
The interface automatically switches from slave to
master after it generates a START condition and
from master to slave in case of arbitration loss or a
STOP generation, allowing then Multi-Master ca-
pability.
Communication Flow
In Master mode, it initiates a data transfer and
generates the clock signal. A serial data transfer
always begins with a start condition and ends with
a stop condition. Both start and stop conditions are
generated in master mode by software.
In Slave mode, the interface is capable of recog-
nising its own address (7 or 10-bit), and the Gen-
eral Call address. The General Call address de-
tection may be enabled or disabled by software.
Data and addresses are transferred as 8-bit bytes,
MSB first. The first byte(s) following the start con-
dition contain the address (one in 7-bit mode, two
in 10-bit mode). The address is always transmitted
in Master mode.
A 9th clock pulse follows the 8 clock cycles of a
byte transfer, during which the receiver must send
an acknowledge bit to the transmitter. Refer to
ure
1.
8
2
C bus. This selection is made by soft-
ACK
9
CONDITION
STOP
VR02119B
2
C bus
73/141
Fig-
2
C