ST72215G2 STMicroelectronics, ST72215G2 Datasheet - Page 63
ST72215G2
Manufacturer Part Number
ST72215G2
Description
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,ADC, 16-BIT TIMERS, SPI, I2C INTERFACES
Manufacturer
STMicroelectronics
Datasheet
1.ST72104G2.pdf
(141 pages)
Specifications of ST72215G2
Emulation Voltage
5.5 V
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SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.4.2 Slave Configuration
In slave configuration, the serial clock is received
on the SCK pin from the master device.
The value of the SPR0 & SPR1 bits is not used for
the data transfer.
Procedure
In this configuration the MOSI pin is a data input
and the MISO pin is a data output.
Transmit Sequence
The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MISO pin most
significant bit first.
The transmit sequence begins when the slave de-
vice receives the clock signal and the most signifi-
cant bit of the data on its MOSI pin.
– For correct data transfer, the slave device
– The SS pin must be connected to a low level
– Clear the MSTR bit and set the SPE bit to as-
must be in the same timing mode as the mas-
ter device (CPOL and CPHA bits). See
4.
signal during the complete byte transmit se-
quence.
sign the pins to alternate function.
Figure
ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx
When data transfer is complete:
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the DR register is read,
the SPI peripheral returns this buffered value.
Clearing the SPIF bit is performed by the following
software sequence:
1. An access to the SR register while the SPIF bit
2.A read to the DR register.
Notes: While the SPIF bit is set, all writes to the
DR register are inhibited until the SR register is
read.
The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
the second SPIF bit in order to prevent an overrun
condition (see
Depending on the CPHA bit, the SS pin has to be
set to write to the DR register between each data
byte transfer to avoid a write collision (see
0.1.4.4
– The SPIF bit is set by hardware
– An interrupt is generated if SPIE bit is set and
is set.
I bit in CCR register is cleared.
).
Section 0.1.4.6
).
Section
63/141
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