71M6533G Maxim, 71M6533G Datasheet - Page 117
71M6533G
Manufacturer Part Number
71M6533G
Description
The Teridian™ 71M6533 and 71M6534 are third-generation polyphase metering systems-on-chips (SoCs) with a 10MHz 8051-compatible MPU core, low-power RTC, flash, and LCD driver
Manufacturer
Maxim
Datasheet
1.71M6533.pdf
(132 pages)
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6.5.5 SPI Slave Port (MISSION Mode)
Rev 2
t
t
t
t
t
t
t
t
t
SPILead
SPILag
SPIcyc
SPIW
SPISCK
SPIDIS
SPIEV
SPISU
SPIH
PSDO
PCSZ
PCLK
PSDI
PCLK cycle time
Enable lead time
Enable lag time
PCLK pulse width:
PCSZ to first PCLK fall
Disable time
PCLK to Data Out
Data input setup time
Data input hold time
High
Low
t
Parameter
SPISCK
t
SPILead
MSB IN
MSB OUT
Figure 48: SPI Slave Port (MISSION Mode) Timing
Table 90: SPI Slave Port (MISSION Mode) Timing
t
SPIW
t
t
SPIH
SPIcyc
Ignore if PCLK is low
when PCSZ falls.
t
SPIEV
Condition
t
SPIW
LSB IN
LSB OUT
Min
15
40
40
10
1
0
2
0
5
t
SPILag
Typ
t
SPIDIS
Max
15
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
117
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