71M6533G Maxim, 71M6533G Datasheet - Page 67

• Manufacturer Part Number: 71M6533G
• Description: The Teridian™ 71M6533 and 71M6534 are third-generation polyphase metering systems-on-chips (SoCs) with a 10MHz 8051-compatible MPU core, low-power RTC, flash, and LCD driver
• Manufacturer: Maxim

2.7 CE/MPU Communication
Figure 30
MPU via shared registers in the I/O RAM and in RAM.
The CE outputs two interrupt signals to the MPU: CE_BUSY and XFER_BUSY, which are connected to
the MPU interrupt service inputs as external interrupts. CE_BUSY indicates that the CE is actively
processing data. This signal will occur once every multiplexer cycle. XFER_BUSY indicates that the CE
is updating data to the output region of the RAM. This will occur whenever the CE has finished generating a
sum by completing an accumulation interval determined by SUM_CYCLES[5:0] * PRE_SAMPS[1:0] samples.
Interrupts to the MPU occur on the falling edges of the XFER_BUSY and CE_BUSY signals.
Refer to
MPU firmware.
Rev 2
Section
shows the functional relationships between the CE and the MPU. The CE is controlled by the
Mux Control
ADC
5.3 CE Interface Description
SAMPLES
(DIO7)
I/O RAM (Configuration RAM)
VAR
CE
Figure 30: MPU/CE Communication
W (DIO6)
PULSES
for additional information on setting up the device using the
SAG CONTROL
INTERRUPTS
XFER BUSY
EXT PULSE
APULSEW
APULSER
CE BUSY
DATA
MPU
DISPLAY (Memory
mapped LCD
segments)
SERIAL
(UART0/1)
EEPROM
(I
DIO
2
C)
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