71M6533G Maxim, 71M6533G Datasheet - Page 56

• Manufacturer Part Number: 71M6533G
• Description: The Teridian™ 71M6533 and 71M6534 are third-generation polyphase metering systems-on-chips (SoCs) with a 10MHz 8051-compatible MPU core, low-power RTC, flash, and LCD driver
• Manufacturer: Maxim

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Depending on the length of the CE program, it may continue running until the end of the last conversion.
CE opcodes are constructed to ensure that all CE code passes consume exactly the same number of
cycles. The result of each ADC conversion is inserted into the XRAM when the conversion is complete.
The CE code is written to tolerate sudden changes in ADC data. The exact clock count when each ADC
value is loaded into RAM is shown in
2.2 System Timing Summary
Figure 19
the two serial output streams. In this example, MUX_DIV[3:0] = 6 and FIR_LEN[1:0] = 1. The duration of
each MUX frame is (M40MHZ/M26MHZ = 00, 10, or 11 assumed):
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An ADC conversion will always consume an integer number of CK32 clocks. Following this is a single
CK32 cycle where the bandgap voltage is allowed to recover from the change in CROSS.
Each CE program pass begins when the ADC0 conversion (slot 0, as defined by SLOT0_SEL) begins.
Figure 20
consisting of 140 CK cycles, will always finish before the next code pass starts.
56
TMUXOUT/RTM
RTM TIMING
ADC TIMING
CE TIMING
ADC EXECUTION
RTM DATA 0 (32 bits)
RTM DATA 1 (32 bits)
RTM DATA 2 (32 bits)
RTM DATA 3 (32 bits)
CE_EXECUTION
1 + MUX_DIV[3:0] * 1, if FIR_LEN[1:0] = 0 (138 CE cycles), complete MUX frame = 7 CK32 cycles
1 + MUX_DIV[3:0] * 2, if FIR_LEN[1:0] = 1 (288 CE cycles) , complete MUX frame = 13 CK32 cycles
1 + MUX_DIV[3:0] * 3, if FIR_LEN[1:0] = 2 (384 CE cycles) , complete MUX frame = 19 CK32 cycles
NOTES:
XFER_BUSY
MUX_SYNC
MUX_SYNC
CE_BUSY
CKTEST
summarizes the timing relationships between the input MUX states, the CE_BUSY signal and
shows that the serial data stream, RTM, begins transmitting at the beginning of state S. RTM,
CK32
RTM
1. ALL DIMENSIONS ARE 4.9152 MHz CK COUNTS.
2. XFER_BUSY OCCURS ONCE EVERY (PRESAMPS * SUM_CYCLES) CODE PASSES.
CK32
Figure 19: Timing Relationship between ADC MUX and Compute Engine
0
FLAG
150
0
ADC0
1
300
CK COUNT = CE_CYCLES + floor((CE_CYCLES + 2) / 4)
30 31
Figure 20: RTM Output Format
Figure
FLAG
INITIATED BY A CE OPCODE AT END OF SUM INTERVAL
ADC1
600
MUX_DIV
19.
0
1
Conversions (MUX_DIV=6 is shown)
30
ADC2
ADC MUX Frame
31
900
FLAG
ADC3
0
1200
1
30
31
ADC4
FLAG
1500
MAX CK COUNT
0
ADC5
1
30 31
1800
Settle
140
Rev 2