71M6533G Maxim, 71M6533G Datasheet - Page 26

• Manufacturer Part Number: 71M6533G
• Description: The Teridian™ 71M6533 and 71M6534 are third-generation polyphase metering systems-on-chips (SoCs) with a 10MHz 8051-compatible MPU core, low-power RTC, flash, and LCD driver
• Manufacturer: Maxim

follows:
•
•
The 71M6533 and 71M6534 have several UART-related registers for the control and buffering of serial
1.4.5 Instruction Set
All instructions of the generic 8051 microcontroller are supported. A complete list of the instruction set
and of the associated op-codes is contained in the 71M653X Software User’s Guide (SUG).
1.4.6 UARTs
The 71M6533 and 71M6534 include a UART (UART0) that can be programmed to communicate with a
variety of AMR modules and other external devices. A second UART (UART1) is connected to the optical
port, as described in the
The UARTs are dedicated 2-wire serial interfaces, which can communicate with an external host processor
at up to 38,400 bits/s (with MPU clock = 1.2288 MHz). The operation of the RX and TX UART0 pins is as
data.
A single SFR register serves as both the transmit buffer and receive buffer (S0BUF, SFR 0x99 for UART0
and S1BUF, SFR 0x9C for UART1). When written by the MPU, SxBUF acts as the transmit buffer, and
when read by the MPU, it acts as the receive buffer. Writing data to the transmit buffer starts the transmission
by the associated UART. Received data are available by reading from the receive buffer. Both UARTs
can simultaneously transmit and receive data.
26
IFLAGS
INTBITS
(INT0 … INT6)
(Alternate Name)
UART0 RX: Serial input data are applied at this pin. Conforming to RS-232 standard, the bytes are
input LSB first.
UART0 TX: This pin is used to output the serial data. The bytes are output LSB first.
Register
0xE8[0]
0xE8[1]
0xE8[2]
0xE8[3]
0xE8[4]
0xE8[5]
0xE8[6]
0xE8[7]
0xF8[6:0] INT6 … INT0
0xF8[7]
Address
SFR
1.5.6 Optical Interface
Only byte operations on the entire INTBITS register should be used when
writing. The byte must have all bits set except the bits that are to be
cleared.
IE_XFER
IE_RTC
FW_COL1
FW_COL0
IE_PB
IE_WAKE
PLL_RISE
PLL_FALL
WD_RST
Bit Field
Name
section.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R
Description
This flag monitors the XFER_BUSY interrupt. It
is set by hardware and must be cleared by the
interrupt handler.
This flag monitors the RTC_1SEC interrupt. It
is set by hardware and must be cleared by the
interrupt handler.
This flag indicates that a flash write was in
progress while the CE was busy.
This flag indicates that a flash write was
attempted when the CE was attempting to
begin a code pass.
This flag indicates that the wake-up pushbutton
was pressed.
This flag indicates that the MPU was awakened
by the autowake timer.
PLL_RISE Interrupt Flag:
Write 0 to clear the PLL_RISE interrupt flag.
PLL_FALL Interrupt Flag:
Write 0 to clear the PLL_FALL interrupt flag.
Interrupt inputs. The MPU may read these bits
to see the status of external interrupts INT0 up
to INT6. These bits do not have any memory
and are primarily intended for debug use.
The WDT is reset when a 1 is written to this bit.
Rev 2