TMPM380FWFG Toshiba, TMPM380FWFG Datasheet - Page 446

• Manufacturer Part Number: TMPM380FWFG
• Manufacturer: Toshiba

Specifications of TMPM380FWFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 12K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 2
• I2c/sio (ch): 2
• Uart/sio (ch): 5
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 18
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

15.5.7 Generating Start and Stop Conditions
SCL line
SDA line
Start condition
When SBInSR<BB> is “0,” writing “1” to SBInCR2 <MST, TRX, BB, PIN> causes the SBI to
generate the start condition on the bus and output 8-bit data. <ACK> must be set to “1” in
advance.
a sequence for generating the stop condition on the bus. The contents of <MST, TRX, BB,
PIN> should not be altered until the stop condition appears on the bus.
SBInSR<BB> can be read to check the bus state. <BB> is set to “1” when the start
condition is detected on the bus (the bus is busy), and set to “0” when the stop condition is
detected (the bus is free).
When <BB> is “1,” writing “1” to <MST, TRX, PIN> and “0” to <BB> causes the SBI to start
Fig 15-10 Generating the Start Condition and a Slave Address
A6
Fig 15-11 Generating the Stop Condition
SCL line
SDA line
1
TMPM380/M382 - 17 / 41 -
A5
2
A4
Slave address and direction bit
3
A3
4
Stop condition
A2
5
A1
6
A0
7
R/W
TMPM380/M382
8
Acknowledgement
signal
9