TMPM380FWFG Toshiba, TMPM380FWFG Datasheet - Page 73

• Manufacturer Part Number: TMPM380FWFG
• Manufacturer: Toshiba

Specifications of TMPM380FWFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 12K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 2
• I2c/sio (ch): 2
• Uart/sio (ch): 5
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 18
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

7 Exceptions
(1) Disabling interrupt by CPU
(2) CPU interrupt registers setting
unexpected interrupt on the way.
Disable the interrupt by the CPU. Configure from the farthest route from the CPU. Then enable the
interrupt by the CPU.
generator, it need to clear the interrupt related data in the clock generator before enable the interrupt.
Clear-Enable register. Each bit of the register, of which default setting is “0” with interrupt disabled, is
assigned to single interrupt factor.
Register.
7.5.2.2 Preparation
When preparing for an interrupt, it is needed to pay attention to the order of configuration to avoid any
Initiating an interrupt or changing its configuration must be implemented in the following order basically.
In order not to generate unnecessary interrupt after condition setting, In case of setting the clock
(1) Disabling interrupt by CPU
(2) CPU registers setting
(3) Preconfiguration 1 (Interrupt from external pin)
(4) Preconfiguration 2 (interrupt from peripheral IP)
(5) Configuring the clock generator
(6) Enabling interrupt by CPU
To make the CPU for not accepting any interrupt, write “1” to the corresponding bit of the Interrupt
assign a interrupt priority level from 0 to 255 by writing to the eight bit field in an Interrupt Priority
The following shows the order of interrupt handling and describe how to configure them.
Priority level 0 is the highest priority level.
(Note)
●CPU register
Interrupt Clear-Enable<m>
●CPU register
Interrupt Priority<m>
(Note)
m: corresponding bit.
m: corresponding bit.
TMPM380/M382 - 18 / 59 -
←
←
“Priority”
“1”(disable interrupt)
TMPM380/M382