TMPM380FWFG Toshiba, TMPM380FWFG Datasheet - Page 540

• Manufacturer Part Number: TMPM380FWFG
• Manufacturer: Toshiba

Specifications of TMPM380FWFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 12K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 2
• I2c/sio (ch): 2
• Uart/sio (ch): 5
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 18
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

DMACC0Configuration
DMACC0Configuration
22.4.2 DMACIntStatus (DMAC Interrupt Status Register)
[Explanation]
[31:2]
[1]
[0]
Bit
a. <IntStatus[1:0]>
Status of the DMAC interrupt generation after passing through the transfer end interrupt enable
register and error interrupt enable register. An interrupt is requested when there is a transfer
error or when the counter completes counting.
DMA transfer error
DMA transfer end
−
IntStatus1
IntStatus0
Symbol
<ITC>
<IE>
Bit
Figure 22-2 Interrupt-related block diagram
TMPM380/M382 - 5 / 26 -
−
R
R
Type
Undefined
0y0
0y0
Reset
Value
DMACIntTCStatus <IntStatusTC0>
DMACRawIntErrorStatus
DMACRawIntTCStatus
Read undefined. Write as zero.
Status of DMAC channel 1 interrupt generation.
0y1: Interrupt requested
0y0: Interrupt not requested
Status of DMAC channel 0 interrupt generation.
0y1: Interrupt requested
0y0: Interrupt not requested
DMACIntErrorStatus
DMACIntStatus <IntStatus0>
(Post-enable transfer error interrupt)
Address = (0x4008_0000) + 0x0000
Description
(Post-enable transfer error interrupt)
(Pre-enable transfer end interrupt)
(Pre-enable transfer error interrupt)
TMPM380/M382