TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 388
TX4939XBG-400
Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet
1.TX4939XBG-400.pdf
(740 pages)
Specifications of TX4939XBG-400
Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456
Available stocks
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Toshiba RISC Processor
PCIC
TX4939
16.3.16. Set Configuration Space
The access to the PCI Configuration space of external PCI devices is explained in section 16-7.
The registers in the PCI registers space (which also has registers corresponding to the standard PCI Configuration Space)
inside the PCI Bridge can be accessed by doing simple GBus read/writes from a GBus master with the address
corresponding to the PCI register space.
16.3.17. PCI Clock
The Clock of PCI Controller logic is designed as asynchronous from the GBUS clock. This internal clock is generated from
the clock connected to the PCICLKIN terminal such way that the internal clock will have minimum skew from the inputted
clock signal at PCICLKIN terminal.
16
16
Rev. 3.1 November 1, 2005
16-24
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