TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 620
TX4939XBG-400
Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet
1.TX4939XBG-400.pdf
(740 pages)
Specifications of TX4939XBG-400
Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456
Available stocks
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Toshiba RISC Processor
I2C
TX4939
22.5. Clock Generator
The Clock Generator generates an internal 4*Fscl clock enable signal that triggers all synchronous elements in the Bit
22
22
Command Controller. It also handles clock stretching needed by some slaves.
22.6. Byte Command Controller
22.6.1. Byte Mode:
The Byte Command Controller handles I2C traffic at the byte level. It takes data from the Command Register and
translates it into sequences based on the transmission of a single byte. By setting the START, STOP, and READ bit in
the Command Register, for example, the Byte Command Controller generates a sequence that results in the generation
of a START signal, the reading of a byte from the slave device, and the generation of a STOP signal. It does this by
dividing each byte operation into separate bit-operations, which are then sent to the Bit Command Controller.
Rev. 3.1 November 1, 2005
22-10
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