TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 79

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Pin Assignment
3.3.6. External Bus Interface Signals
3.3.7. ISA Interface Signals
Rev. 3.1 November 1, 2005
External Bus Signals
Signal Name
SADB[15:0]
BE[1:0]*
ACE*
SA[5:0]
SYSCLK
NRCE* (CE[0])
CE[3:1]*
OE*
SWE*
ACK*
(READY)
DMAREQ[2:0]
DMAACK[2:0]
DMADONE*
Signals for NAND Controller
NDCE*
NDLA
NDRB*
NDCLE
NDALE
NDCS0
NDCS1
NDRE*
NDWE*
External Bus Signals
Signal Name
SADB[15:0]
SA[21:0]
BHE*
IOW*
IOR*
WAIT
CS*
I/O
I/O
PU
Output
Output
I/O
PU
Output
Output
Output
Output
Output
Input
PU
Input
PU
I/O
PU
I/O
PU
Output
Output
PU
Input
(Output)
(Output)
(Output)
(Output)
(Output)
(Output)
I/O
I/O
PU
Output
Output
Output
Output
Input
Output
Function
External Bus Address Data Bus (Lower 16-bit)
16/8-bit data bus for External bus.
external latch devices.
Byte Enable Signal
Access Control signal for upper and lower byte on External bus.
Address Clock Enable
This is the Latch Enable signal for the upper ADDR address.
Lower Address Bits
This is the lower address for External bus access.
Configuration.
System Clock
This is a device clock for external I/O.
Chip Enable, dedicated for "NOR" Flash access as boot device.
Chip Enables for generic use
Output Enable
This is the Output Enable signal for ROM, SRAM, or I/O devices.
Write Enable
This is the Write Enable signal for SRAM and I/O devices.
Acknowledge
This is the Flow Control signal.
DMA Request
This is the DMA Transfer Request signal from external I/O devices.
DMA Acknowledge
This is the DMA Transfer Acknowledge signal for external I/O devices.
used for the Boot Configuration.
DMA Done
This signal functions either as an output signal that signals the end of DMA transfer or
as an input signal for ending DMA transfer.
NAND Flash Chip Enable (NAND CE*)
NAND Flash Control Signal Latch Enable
NAND Flash Ready/Busy (NAND R/B)
NAND CLE that can be generated from SA[0] latched by NDLA
NAND ALE that can be generated from SA[1] latched by NDLA
Extended NAND chip select, that can be generated from SA[2] latched by NDLA
Extended NAND chip select, that can be generated from SA[3] latched by NDLA
NAND RE* that can be generated from SA[4] latched by NDLA
NAND WE* that can be generated from SA[5] latched by NDLA
Function
ISA Data Bus (16-bit)
Address [21:6] will appear on this bus to latch by external latch devices.
ISA Address Bus
SA[5:0] is connecting direct to TX4939
SA[21:6] is connecting directly to external address latch devices.
Byte High Enable
IO Write Command.
IO Read Command.
WAIT command.
for slow ISA device.
ISA Chip Select.
- Together with SA[0] to determine if this is a 8-bit or 16-bit cycle
ISA device use this signal to drag out the cycle, this signal is needed
3-7
Address [21:6] will appear on this bus to latch by
These pins are also used for Boot
Toshiba RISC Processor
This pin also
TX4939
3
3